MF10ACWM National Semiconductor, MF10ACWM Datasheet - Page 20

• Manufacturer Part Number: MF10ACWM
• Manufacturer: National Semiconductor

Specifications of MF10ACWM

• Architecture: Switched Capacitor
• Filter Type: Universal
• Cutoff Frequency: 30KHz
• Dual Supply Voltage (typ): ±5V
• Power Supply Requirement: Single/Dual
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: SOIC W
• Lead Free Status / Rohs Status: Not Compliant

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3.0 Applications Information
The MF10 is a general-purpose dual second-order state
variable filter whose center frequency is proportional to the
frequency of the square wave applied to the clock input
(f
the filter center frequency f
f
varied over a wide frequency range by adjusting the clock
frequency. If desired, the f
external resistors as in Figures 9, 10, 11, 13, 14, 15 . The
filter Q and gain are determined by external resistors.
All of the five second-order filter types can be built using
either section of the MF10. These are illustrated in Figure 1
through Figure 5 along with their transfer functions and some
related equations. Figure 6 shows the effect of Q on the
shapes of these curves. When filter orders greater than two
are desired, two or more MF10 sections can be cascaded.
3.1 DESIGN EXAMPLE
In order to design a second-order filter section using the
MF10, we must define the necessary values of three param-
eters: f
band gain; and the filter’s Q. These are determined by the
characteristics required of the filter being designed.
As an example, let’s assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at DC, and 1000 Hz cutoff frequency. As the system
order is four, it is realizable using both second-order sections
of an MF10. Many filter design texts include tables that list
the characteristics (f
filter sections needed to synthesize a given higher-order
filter. For the Chebyshev filter defined above, such a table
yields the following characteristics:
f
f
For unity gain at DC, we also specify:
H
H
The desired clock-to-cutoff-frequency ratio for the overall
filter of this example is 100 and a 100 kHz clock signal is
available. Note that the required center frequencies for the
two second-order sections will not be obtainable with
clock-to-center-frequency ratios of 50 or 100. It will be nec-
essary to adjust
±
CLK
0A
0B
CLK
6%) by using a crystal clock oscillator, or can be easily
0A
0B
= 529 Hz Q
= 993 Hz Q
/100 or f
= 1
= 1
). By connecting pin 12 to the appropriate DC voltage,
0
, the filter section’s center frequency; H
CLK
A
B
/50. f
= 0.785
= 3.559
O
O
and Q) of each of the second-order
can be very accurately set (within
O
CLK
can be made equal to either
/f
O
ratio can be altered by
0
, the pass-
20
externally. From Table 1 , we see that Mode 3 can be used to
produce a low-pass filter with resistor-adjustable center fre-
quency.
In most filter designs involving multiple second-order stages,
it is best to place the stages with lower Q values ahead of
stages with higher Q, especially when the higher Q is greater
than 0.707. This is due to the higher relative gain at the
center frequency of a higher-Q stage. Placing a stage with
lower Q ahead of a higher-Q stage will provide some attenu-
ation at the center frequency and thus help avoid clipping of
signals near this frequency. For this example, stage A has
the lower Q (0.785) so it will be placed ahead of the other
stage.
For the first section, we begin the design by choosing a
convenient value for the input resistance: R
absolute value of the passband gain H
1 by choosing R
If the 50/100/CL pin is connected to mid-supply for nominal
100:1 clock-to-center-frequency ratio, we find R
The resistors for the second section are found in a similar
fashion:
The complete circuit is shown in Figure 16 for split
power supplies. Supply bypass capacitors are highly
recommended.
4A
such that: R
4A
= −H
OLPA
OLPA
R
is made equal to
1A
1A
= R
2A
= 20k. The
1A
by:
= 20k.
±
5V