IS42S16400C1-7TL ISSI, Integrated Silicon Solution Inc, IS42S16400C1-7TL Datasheet - Page 34

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IS42S16400C1-7TL

Manufacturer Part Number
IS42S16400C1-7TL
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet

Specifications of IS42S16400C1-7TL

Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS42S16400C1-7TL
Manufacturer:
ISSI
Quantity:
4 889
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
IS42S16400C1
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
34
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing CAS latency later.
The PRECHARGE to bank n will begin after t
where t
The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m.
Internal States
COMMAND
Internal States
ADDRESS
COMMAND
ADDRESS
BANK m
WR
BANK n
BANK m
BANK n
begins when the READ to bank m is registered.
CLK
CLK
DQ
DQ
Page Active
T0
NOP
Page Active
T0
NOP
WRITE - AP
BANK n,
WRITE - AP
T1
BANK n
COL a
BANK n,
D
Page Active
T1
BANK n
COL a
D
IN
WRITE with Burst of 4
IN
a
a
Page Active
WRITE with Burst of 4
T2
D
NOP
D
T2
IN
NOP
IN
a+1
WR
a+1
Integrated Silicon Solution, Inc. — www.issi.com —
is met,
READ - AP
BANK m,
BANK m
T3
COL b
T3
D
NOP
Interrupt Burst, Write-Back
IN
a+2
t
CAS Latency - 3 (BANK m)
WR
4. Interrupted by a WRITE (with or without auto precharge):
- BANK n
AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
t
m is registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to bank m.
WR
T4
WRITE - AP
NOP
BANK m,
BANK m
T4
COL b
D
READ with Burst of 4
Interrupt Burst, Write-Back
is met, where t
IN
b
t
WR
WRITE with Burst of 4
- BANK n
T5
NOP
T5
D
NOP
IN
b+1
WR
begins when the WRITE to bank
T6
NOP
T6
D
NOP
D
Precharge
IN
t
OUT
RP - BANK n
b+2
b
t
Precharge
RP - BANK n
DON'T CARE
DON'T CARE
T7
NOP
D
T7
D
NOP
Precharge
OUT
Write-Back
IN
t
RP - BANK m
b+3
t
ISSI
b+1
RP - BANK m
1-800-379-4774
10/25/05
Rev. E
®

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