IS43R32400A-6B ISSI, Integrated Silicon Solution Inc, IS43R32400A-6B Datasheet - Page 10

• Manufacturer Part Number: IS43R32400A-6B
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32400A-6B

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 850ps
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 420mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IS43R32400A
DC ELECTRICAL CHARACTERISTICS
Notes:
1.Operating outside the “Absolute Maximum Ratings” may lead to temporary or permanent device failure.
2.Power up sequence describe in “Initialization” section.
3. All voltages are referenced to V
10
Symbol Parameter
I
I
I
I
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
0
1
2
2
3
3
4
4
5
6
7
N
N
R
W
P
P
Operating Current
Operating Current
Precharge Power-Down
Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Burst Read
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Burst Write
SS
.
Test Condition
One bank operation; Active-Precharge; DQ, DM and DQS
inputs change once per clock cycle; Address and Control
inputs change once per two clock cycles; tRC = tRC (min);
tCK = tCK (min)
One bank operation; Active-Read-Precharge; BL = 4; CL = 4;
Address and Control inputs change once per clock cycle;
tRCDRD = 4 x tCK; tRC = tRC (min); tCK = tCK (min);
IOUT = 0mA;
All banks Idle; tCK = tCK (min); CKE = Low
All banks idle; Address and control inputs change once per
clock cycle; CKE = High; CS = High (Deselect); VIN = VREF
for DQ, DQS, and DM; tCK = tCK (min)
One bank Active; CKE = Low; tCK = tCK (min)
One bank Active; CS = High; CKE = High; Address and
Control inputs change once per clock cycle; DQ, DQS, and
DM change twice per clock cycle; tRC = tRC (max);
tCK = tCK (min)
One bank Active; BL = 2; Address and Control inputs
change once per clock cycle; tCK = tCK (min); IOUT = 0mA
One bank Active; BL = 2; Address and Control inputs change
once per clock cycle; DQ, DQS, DM change twice per clock
cycle; tCK = tCK (min)
tRC = tRFC (min); tCK = tCK (min)
CKE
Four bank interleaved Reads with Auto Precharge; BL = 4;
Address and Controls inputs change per Read, Write, or
Active command; tRC = tRC (min); tCK = tCK (min)
≤
0.2V; tCK = tCK (min)
(V
DD
= 2.5V +/- 5%, T
Integrated Silicon Solution, Inc. — 1-800-379-4774
A
= 0
o
C to +70
o
C)
ISSI
160
240
100
420
270
280
550
40
80
40
3
Rev. 00D
02/15/06
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
®