LM74-3EVAL National Semiconductor, LM74-3EVAL Datasheet - Page 10

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LM74-3EVAL

Manufacturer Part Number
LM74-3EVAL
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of LM74-3EVAL

Lead Free Status / Rohs Status
Not Compliant
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1.0 Functional Description
1.5 INTERNAL REGISTER STRUCTURE
The LM74 has three registers, the temperature register, the
configuration register and the manufacturer’s/device identifi-
cation register. The temperature and manufacturer’s/device
identification registers are read only. The configuration reg-
ister is write only.
1.5.1 Configuration Register
(Selects shutdown or continuous conversion modes):
D0–D15 set to XX FF hex enables shutdown mode.
D0–D15 set to 00 00 hex sets Continuous conversion mode.
Note: setting D0-D15 to any other values may place the LM74 into a manufacturer’s test mode, upon which the LM74 will stop
responding as described. These test modes are to be used for National Semiconductor production testing only. See Section 1.2
Serial Bus Interface for a complete discussion.
1.5.2 Temperature Register (after power-up, before first complete temperature conversion)
D0–D1: Undefined. TRI-STATE will be output on SI/0.
D2–D15: Power-on Reset (POR) values.
1.5.3 Temperature Register (after completion of first temperature conversion)
D0–D1: Undefined. TRI-STATE will be output on SI/0.
D2: High.
D3–D15: Temperature Data. One LSB = 0.0625˚C. Two’s complement format.
1.5.4 Manufacturer’s Device ID Register
D0–D1: Undefined. TRI-STATE will be output on SI/0.
D2–D15: Manufacturer’s/Device ID Data. This register is accessed whenever the LM74 is in shutdown mode.
(Write Only):
(Read Only):
(Read Only):
(Read Only):
MSB
D15
D15
D15
D15
X
1
1
Bit 11 Bit 10
D14
D14
D14
D14
X
1
0
D13
D13
D13
D13
X
1
0
Bit 9
D12
D12
D12
D12
X
1
0
Bit 8
D11
D11
D11
D11
X
1
0
Bit 7
D10
D10
D10
D10
X
1
0
(Continued)
Bit 6
D9
D9
D9
D9
X
1
0
Bit 5
D8
D8
D8
D8
X
1
0
10
Bit 4
D7
D7
D7
D7
0
0
Bit 3
D6
D6
D6
D6
0
0
Bit 2
D5
D5
D5
D5
0
0
Bit 1
D4
D4
D4
D4
Shutdown
0
0
LSB
D3
D3
D3
D3
0
0
D2
D2
D2
D2
0
1
0
D1
D1
D1
D1
X
X
X
D0
D0
D0
D0
X
X
X