EVAL-AD9830EB Analog Devices Inc, EVAL-AD9830EB Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD9830EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9830EB

• Lead Free Status / Rohs Status: Not Compliant

Preliminary Technical Data
SET-UP CONDITIONS
Care should be taken before applying power and signals to the
evaluation board to ensure that all link positions are as per the
required operating mode. Table 1 shows the position in which
all the links are set when the evaluation board is sent out.
Link No.
LK1
LK2
LK3
LK4
LK5
SW
EVALUATION BOARD INTERFACING
Interfacing to the evaluation board is via a 36-way centronics
female connector, J1. The pinout for the J1 connector is
shown in Figure 1 and its pin designations are given in Table
2.
Figure1. Pin Configuration for the 36-Way Connector, J1.
36
1
Table 1. Initial Link and Switch Positions
Function
LK1 is arranged so that PSEL1 is tied to
SW.
LK2 is arranged so that PSEL0 is tied to
SW.
LK3 is arranged so that FSELECT is tied to
SW.
LK4 is connected so that
DVDD and, hence, the AD9830 is powered
up.
REFOUT is tied to REFIN.
All the SW switches are arranged so that
DVDD is selected.
SLEEP
19
18
is tied to
- 3 -
36-Way Connector Pin Description
DGND
DB0 - DB7
LOAD
LATCH
WR
RESET
Digital Ground. These lines are connected
When the 8 MSBs of the 16 bit word are
The 8 LSBs of the 16 bit word are held in
to the digital ground plane on the evaluation
board.
Data Bit 0 to Data Bit 7. Data transfers
from the PC are 8 bits wide. Therefore, the
16 bit word is split into two 8 bit words.
For each write operation, there are 3
transfers of data from the PC: the 8 MSBs
of the 16 bit word, the 8 LSBs of the 16 bit
word and the address data to bits A0, A1
and A2. The AD9830 accepts CMOS logic.
written to the evaluation board from the PC,
the word is held in a latch, a 74HC574 latch.
This latch latches in the data on the rising
edge of the CK signal. The LOAD signal
provides this rising edge.
the latch U3. The rising CK edge to this
part is provided by LATCH.
Write. This is an active low logic input
which is used to write the digital data to the
AD9830. When the address bits A0, A1 and
A2 are being written to, the
generated also. On the rising edge of
the AD9830 reads in the 16 bit word from
the 74HC574 latches along with the address
values.
Reset. When
AD9830 is reset. On reset, the phase
accumulator is reset to zero.
RESET
EVAL-AD9830EB
is taken low, the
AD7002
WR
signal is
WR
REV 0
,