9248BF-50LF IDT, Integrated Device Technology Inc, 9248BF-50LF Datasheet

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9248BF-50LF

Manufacturer Part Number
9248BF-50LF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 9248BF-50LF

Number Of Elements
2
Supply Current
180mA
Pll Input Freq (min)
11MHz
Pll Input Freq (max)
16MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
SSOP
Output Frequency Range
14.318 to 100MHz
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Pin Count
28
Lead Free Status / Rohs Status
Compliant
Frequency Timing Generator for Pentium II Systems
Block Diagram
General Description
Power Groups
0278I—06/03/03
The ICS9248-50
Integrated
Circuit
Systems, Inc.
ICS9248-50
Features
Generates the following system clocks:
- 2 CPU (2.5V) up to 100MHz.
- 6 PCI (3.3V) @ 33.3MHz (Includes one free
running).
- 2 REF clks (3.3V) at 14.318MHz.
Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
Supports Spread Spectrum modulation for CPU and
PCI clocks, 0.5% down spread
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
28-pin (209 mil) SSOP package
Pin Configuration
28-Pin SSOP
ICS9248-50

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9248BF-50LF Summary of contents

Page 1

Integrated Circuit Systems, Inc. Frequency Timing Generator for Pentium II Systems General Description The ICS9248-50 Block Diagram Power Groups 0278I—06/03/03 Features • Generates the following system clocks CPU (2.5V 100MHz PCI (3.3V) @ 33.3MHz ...

Page 2

ICS9248-50 Pin Descriptions Pin number Pin name 1 GNDREF PCICLK_F 5,6,9,10,11 PCICLK (1:5) 7 GNDPCI 8 VDDPCI 12 VDD48 13 48 MHz 14 TS#/48/24MHz 15 GND48 16 SEL 100/66# 17 PD# 18 CPU_STOP# 19 VDD ...

Page 3

Select Functions ...

Page 4

ICS9248-50 CPU_STOP# Timing Diagram Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-50. 3. All other clocks continue ...

Page 5

PD# Timing Diagram Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248. 3. The shaded ...

Page 6

ICS9248-50 Absolute Maximum Ratings Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . ...

Page 7

Electrical Characteristics - CPUCLK 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B 1 ...

Page 8

ICS9248-50 Electrical Characteristics - PCICLK 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 1 ...

Page 9

General Layout Precautions: Notes: Capacitor Values: 0278I—06/03/03 9 ICS9248-50 ...

Page 10

ICS9248-50 Ordering Information 9248yF-50-T XXXX PPP - T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) Package Type Revision Designator Device Type (consists ...

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