IDT49C466APQF IDT, Integrated Device Technology Inc, IDT49C466APQF Datasheet
![](/photos/31/30/313071/208pin_pqfp_sml.jpg)
IDT49C466APQF
Specifications of IDT49C466APQF
Available stocks
Related parts for IDT49C466APQF
IDT49C466APQF Summary of contents
Page 1
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT FEATURES: − 64-bit wide Flow-thruEDC™ − Separate System and Memory Data Input/Output Buses • Error Detect Time: 10ns • Error Correct Time: 15ns − Corrects all single bit errors; Detects all ...
Page 2
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT JECTIO MUX IN KBIT BYTE MUX MUX MUX 2 COMMERCIAL TEMPERATURE RANGE MUX MUX BFF W BEF W ...
Page 3
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN CONFIGURATION 208 1 GND MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 SDOLE MOE MDILE ...
Page 4
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN DESCRIPTION Pin Name I/O Data Buses SD I/O System Data Bus bidirectional 64-bit bus interfacing to the system or CPU. When System Output Enable, SOE, 0-63 is HIGH ...
Page 5
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN DESCRIPTION (cont.) Pin Name I/O RBSEL I Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output latch). When LOW, the MD output ...
Page 6
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DETAILED DESCRIPTION — 64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART Generated Checkbits Parity CB0 Even (XOR) CB1 Even (XOR) CB2 Odd (XNOR) CB3 Odd (XNOR) CB4 Even (XOR) CB5 Even ...
Page 7
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DETAILED DESCRIPTION — 64-BIT SYNDROME DECODE TO BIT-IN-ERROR HEX S7 S6 Syndrome S5 Bits S4 HEX ...
Page 8
... The generated checkbits are X-ORed with the input checkbits to produce the syndrome word. This is sent to the error correction circuitry which generates the corrected data (normal mode). The corrected data is output to the SD bus via either of two data paths ...
Page 9
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT R/W FIFO Operation At Boundaries In the 49C466 the write pointer is incremented on every FIFO write. Similarly the read pointer is incremented on every FIFO read. In most cases on ...
Page 10
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT Partial Word Write/Byte Merge Writing a word shorter than 64 bits to memory is treated as a special case. The checkbits generated for a data word shorter than 64 bits and ...
Page 11
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT Fig 3. Memory Initialization using Diagnostic Output/Error Data Output Mode DIAGNOSTIC OUTPUT DATA FORMAT rro r Syn drom e ...
Page 12
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT ABSOLUTE MAXIMUM RATINGS Symbol Rating V Power Supply Voltage CC V Terminal Voltage with TERM Respect to Ground T Temperature Under Bias BIAS T Storage Temperature STG I DC Output Current ...
Page 13
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC PARAMETERS PROPAGATION DELAY TIMES Number Parameter From Input GENERATE (WRITE) PARAMETERS Without Write FIFO BEn BEn Pxin PPE 4 t SDin SC ...
Page 14
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PROPAGATION DELAY TIMES FROM LATCH ENABLES Number Parameter From Input 21 t MDILE (Lo-Hi) MLE 22 t MDILE (Lo-Hi) MLME 23 t MDILE (Lo-Hi) MLP 24 t MDILE (Lo-Hi) MLS 25 ...
Page 15
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT BYTE MERGE TIMES Number Parameter From Input 36 t SCLK (Lo-Hi) SCM 37 t MDOLE (Hi-Lo) MDM 38 t RBSEL RBM NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa. ENABLE ...
Page 16
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT SET-UP AND HOLD TIMES (1) Number Parameter From Input 52 t CBI Set-up CMLS 53 t CBI Hold CMLH 54 t MDIN Set-up MMLS 55 t MDIN Hold MMLH 56 t ...
Page 17
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MINIMUM PULSE WIDTH (1) Number Parameter From Input 85 t Min. RS1 LOW time Min. MDILE HIGH time MLE 87 t Min. MDOLE LOW time MDOLE 88 t ...
Page 18
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load SD0-15 SCLK MEN W BSEL SOE SCLK (W CLK) SD0-63 W BEN W ...
Page 19
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT M CLK (RCLK) W BREN W BEF W BSEL SD OLE D0-63 CBSYN0-7 write SCLK (W CLK) Figure 6. WFIFO Read and Checkbit Generate Timing (Write Cycle) read ...
Page 20
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT RBSEL 0- out CBI0 DILE write M C ...
Page 21
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT SCLK (R CLK) RBREN RBEF M CLK (W C LK) RBSEL SOE BE 0-7 SD 0-63 P 0-7 read t ENH t ENS write t SKEW 2 ...
Page 22
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT CLK (SCLK / M CLK ATA (SD /MD) W CLK (SC LK/MC LK) t ENS BU FFER ENABLE (W BEN/ RBEN) t RSF FIFO RESET ...
Page 23
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT BE0-7 SOE SD0-63 SDILE SDOLE M D0- MDILE MDOLE RBSEL W BSEL NOTE not a propagation delay. For partial word write operations t MMOE SDin Dy ...
Page 24
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT BE0-7 SOE SD dum m y write SCLK MCLK t ENS W BEN W BREN W BSEL M D RBEN t ENS RBREN RBSE Figure 12. Partial Word ...
Page 25
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT invalid data SD 0-63 dum m y write SCLK (W CLK) t RSS RS1 BEF M CLK (RCLK) W BREN Figure 13. Write FIFO Write Timing with ...
Page 26
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT TEST CIRCUITS FOR ALL OUTPUTS OUT V IN Pulse D.U.T. Generator R T SET-UP, HOLD, AND RELEASE TIMES DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ...
Page 27
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT ORDERING INFORMATION IDT 49C466 X XX Device Type Speed Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 X Process/ Tem perature Range Blank Com m ercial (0 ° C ...