MC74ACT174DR2G ON Semiconductor, MC74ACT174DR2G Datasheet - Page 2
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MC74ACT174DR2G
Manufacturer Part Number
MC74ACT174DR2G
Description
Manufacturer
ON Semiconductor
Datasheet
1.MC74ACT174DR2G.pdf
(9 pages)
Specifications of MC74ACT174DR2G
Logic Family
ACT
Technology
CMOS
Number Of Bits
6
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Polarity
Non-Inverting
Operating Supply Voltage (typ)
5V
Package Type
SOIC
Propagation Delay Time
11.5ns
Low Level Output Current
24mA
High Level Output Current
-24mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Compliant
edge−triggered D flip−flops with individual D inputs and Q
outputs. The Clock (CP) and Master Reset (MR) are
common to all flip−flops. Each D input’s state is transferred
to the corresponding flip−flop’s output following the
MAXIMUM RATINGS*
V
V
V
I
I
I
T
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
IN
OUT
CC
stg
mended Operating Conditions.
The
CC
IN
OUT
Symbol
MR
MC74AC174/74ACT174
CP
FUNCTIONAL DESCRIPTION
D
5
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC V
Storage Temperature
D
CP
CD
CC
Q
or GND Current per Output Pin
Q
5
NOTE:
D
4
D
CP
consists
CD
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
Q
Q
4
Parameter
Figure 2. Logic Symbol
Figure 3. Logic Diagram
of
D
http://onsemi.com
3
CP
MR
Q
D
D
CP
six
0
0
CD
D
Q
1
1
Q
D
Q
2
2
2
Q
D
Q
LOW−to−HIGH Clock (CP) transition. A LOW input to the
Master Reset (MR) will force all outputs LOW independent
of Clock or Data inputs. The MC74AC174/ 74ACT174 is
useful for applications where the true output only is required
and the Clock and Master Reset are common to all storage
elements.
3
3
3
Q
D
4
4
D
D
Q
2
5
5
D
CP
CD
Q
Q
2
D
1
D
CP
−0.5 to V
−0.5 to V
CD
−0.5 to +7.0
−65 to +150
Q
Value
±20
±50
±50
Q
CC
CC
1
+0.5
+0.5
D
0
D
CP
CD
Q
Unit
mA
mA
mA
°C
V
V
V
Q
0