MAX512CSD+T Maxim Integrated Products, MAX512CSD+T Datasheet - Page 10

• Manufacturer Part Number: MAX512CSD+T
• Description: IC DAC 8BIT TRIPLE SERIAL 14SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX512CSD+T

• Settling Time: 70µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 3
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
When programmed to shutdown mode, the outputs of
DAC A and B go into a high-impedance state. Virtually
no current flows into or out of the buffer amplifiers in
that state. The output of DAC C goes to 0V when shut
down. In shutdown mode, the REF_ inputs are high
impedance (2MΩ typ) to conserve current drain from
the system reference; therefore, the system reference
does not have to be powered down. The logic output
LOUT remains active in shutdown.
Coming out of shutdown, the DAC outputs return to the
values kept in the registers. The recovery time is equiv-
alent to the DAC settling time.
The
= 0), DACs A and B are set to full scale (FFhex) and
active, while DAC C is set to zero code (00hex) and
active. The 16-bit serial register is cleared to 0000hex.
LOUT is reset to zero.
An active-low chip select (
to receive data from the serial data input. Data is
clocked into the shift register on every rising edge of
the serial clock signal (SCLK). The clock frequency can
be as high as 5MHz.
Data is sent MSB first and can be transmitted in one
16-bit word. The write cycle can be interrupted at any
time when
two 8-bit-wide transfers. After clocking all 16 bits into
Figure 2. MAX512/MAX513 3-Wire Serial-Interface Timing Diagram
10
–
R
______________________________________________________________________________________
—
E
—
S
—
E
—
SCLK
SDIN
–
T
–
C
—
CS
input is active low. When asserted (
S
–
is kept active (low) to allow, for example,
Q2
Q1
C
–
—
S
–
SC
) enables the shift register
(CONTROL BYTE)
SB
Serial Interface
SA
Shutdown Mode
LC
LB
LA
–
R
—
Reset
E
—
S
—
E
—
T
–
the input shift register, the rising edge of
the DAC outputs, the shutdown status, and the status of
the logic output. Because of their single buffered struc-
ture, DACs cannot be simultaneously updated to differ-
ent digital values.
Table 1. Input Shift Register
**Clocked in last.
**Clocked in first.
OPTIONAL
D7
D6
D5
Q2**
B0*
LC
SA
SB
SC
Q1
B1
B2
B3
B4
B5
B6
B7
LA
LB
(DATA BYTE)
D4
D3
D2
DAC Data Bit 0 (LSB)
DAC Data Bit 1
DAC Data Bit 2
DAC Data Bit 3
DAC Data Bit 4
DAC Data Bit 5
DAC Data Bit 6
DAC Data Bit 7 (MSB)
Load Reg DAC A, Active High
Load Reg DAC B, Active High
Load Reg DAC C, Active High
Shut Down DAC A, Active High
Shut Down DAC B, Active High
Shut Down DAC C, Active High
Logic Output
Uncommitted Bit
D1
D0
INSTRUCTION
EXECUTED
–
C
—
S
–
updates