72265LA10PF Integrated Device Technology (Idt), 72265LA10PF Datasheet - Page 14

• Manufacturer Part Number: 72265LA10PF
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72265LA10PF

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

that shifts the last word from the FIFO memory to the outputs. OR goes
HIGH only with a true read (RCLK with REN = LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing
(FWFT Mode), for the relevant timing information.
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are
written to the FIFO. The PAF will go LOW after (8,192-m) writes for the
IDT72255LA and (16,384-m) writes for the IDT72265LA. The offset “m” is
the full offset value. The default setting for this value is stated in the footnote
of Table 1.
IDT72255LA and (16,385-m) writes for the IDT72265LA, where m is the
full offset value. The default setting for this value is stated in the footnote of
Table 2.
and FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
In IDT Standard mode, EF is a double register-buffered output. In FWFT
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
In FWFT mode, the PAF will go LOW after (8,193-m) writes for the
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
EF/OR is synchronous and updated on the rising edge of RCLK.
14
LOW when there are n words or less in the FIFO. The offset “n” is the
empty offset value. The default setting for this value is stated in the footnote
of Table 1.
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
dard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
FIFO beyond half-full sets HF LOW. The flag remains LOW until the differ-
ence between the write and read pointers becomes less than or equal to
half of the total depth of the device; the rising RCLK edge that accomplishes
this condition sets HF HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 8,192
for the IDT72255LA and 16,384 for the IDT72265LA.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 8,193 for the
IDT72255LA and 16,385 for the IDT72265LA.
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
In FWFT mode, the PAE will go LOW when there are n+1 words or less
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Stan-
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
17
) are data outputs for 18-bit wide data.
0
-Q
17
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009