XC3S1200E-4FG320C Xilinx Inc, XC3S1200E-4FG320C Datasheet - Page 149
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XC3S1200E-4FG320C
Manufacturer Part Number
XC3S1200E-4FG320C
Description
FPGA Spartan®-3E Family 1.2M Gates 19512 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin FBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-4FG320C
Package
320FBGA
Family Name
Spartan®-3E
Device Logic Cells
19512
Device Logic Units
2168
Device System Gates
1200000
Number Of Registers
17344
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
250
Ram Bits
516096
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Miscellaneous DCM Timing
Table 110: Miscellaneous DCM Timing
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
DCM_RST_PW_MIN
DCM_RST_PW_MAX
DCM_CONFIG_LAG_TIME
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex-4 DCM_RESET specfication.This specification does not apply for Spartan-3E FPGAs.
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.
R
Symbol
(1)
(2)
(3)
Minimum duration of a RST pulse width
Maximum duration of a RST pulse width
Maximum duration from V
configuration successfully completed (DONE pin goes
High) and clocks applied to DCM DLL
www.xilinx.com
Description
CCINT
applied to FPGA
DC and Switching Characteristics
Min
N/A
N/A
N/A
N/A
3
Max
N/A
N/A
N/A
N/A
-
seconds
seconds
minutes
minutes
CLKIN
cycles
Units
149
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