8308AGILF Integrated Device Technology (Idt), 8308AGILF Datasheet

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8308AGILF

Manufacturer Part Number
8308AGILF
Description
Clock Driver 2-IN LVCMOS/LVTTL 24-Pin TSSOP Tube
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.8308AGILFT.pdf (16 pages)

Specifications of 8308AGILF

Package
24TSSOP
Configuration
1 x 2:1
Input Signal Type
HCSL|LVCMOS|LVDS|LVHSTL|LVPECL|LVTTL|SSTL
Maximum Output Frequency
350 MHz
Operating Supply Voltage
2.5|3.3 V

Available stocks

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Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
8308AGILF
Manufacturer:
IDT
Quantity:
124
B
ICS8308AGI REVISION C MARCH 23, 2011
G
The ICS8308I is a low-skew, 1-to-8 Fanout Buffer. The ICS8308I
has two selectable clock inputs. The CLK, nCLK pair can accept
most differential input levels. The LVCMOS_CLK can accept
LVCMOS or LVTTL input levels. The low impedance LVCMOS/
LVTTL outputs are designed to drive 50
terminated transmission lines. The effective fanout can be
increased from 8 to 16 by utilizing the ability of the outputs to
drive two series terminated transmission lines.
The ICS8308I is characterized for 3.3V core/3.3V output,
3.3V core/2.5V output or 2.5V core/2.5V output operation.
Guaranteed output and part-part skew characteristics make
the 8308I ideal for those clock distribution applications requiring
well defined performance and repeatability.
LVCMOS_CLK
LOCK
ENERAL
CLK_SEL
CLK_EN
nCLK
CLK
OE
D
Pullup
Pullup
Pullup
Pulldown
Pullup
Pullup
IAGRAM
D
ESCRIPTION
1
0
Low Skew, 1-to-8 Differential/LVCMOS-to-
LVCMOS Fanout Buffer
D
LE
Q
series or parallel
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
F
Eight LVCMOS/LVTTL outputs, (7
Selectable LVCMOS_CLK or differential CLK, nCLK inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum Output Frequency: 350MHz
Output Skew: (3.3V± 5%): 100ps (maximum)
Part to Part Skew: (3.3V± 5%): 1ns (maximum)
Supply Voltage Modes:
(Core/Output)
3.3V/2.5V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
EATURES
3.3V/3.3V
2.5V/2.5V
P
4.4mm x 7.8mm x 0.925mm body package
IN
LVCMOS_CLK
A
CLK_SEL
SSIGNMENT
CLK_EN
24-Lead, 173-MIL TSSOP
nCLK
GND
GND
V
CLK
V
DDO
OE
Q0
Q1
DD
ICS8308I
G Package
1
2
3
4
5
6
7
8
9
10
11
12
Top View
24
23
22
21
20
19
18
17
16
15
14
13
2011 Integrated Device Technology, Inc.
V
Q2
GND
Q3
V
Q4
GND
Q5
V
Q6
GND
Q7
typical output impedance)
DDO
DDO
DDO
DATA SHEET
ICS8308I

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8308AGILF Summary of contents

Page 1

Low Skew, 1-to-8 Differential/LVCMOS-to- LVCMOS Fanout Buffer G D ENERAL ESCRIPTION The ICS8308I is a low-skew, 1-to-8 Fanout Buffer. The ICS8308I has two selectable clock inputs. The CLK, nCLK pair can accept most differential input levels. The LVCMOS_CLK can accept ...

Page 2

ICS8308I Data Sheet ABLE IN ESCRIPTIONS ...

Page 3

ICS8308I Data Sheet BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...

Page 4

ICS8308I Data Sheet T 4D ABLE HARACTERISTICS ...

Page 5

ICS8308I Data Sheet T 4F ABLE HARACTERISTICS ...

Page 6

ICS8308I Data Sheet T 5B ABLE HARACTERISTICS ...

Page 7

ICS8308I Data Sheet T 5C ABLE HARACTERISTICS ...

Page 8

ICS8308I Data Sheet P ARAMETER 1.65V± DDO LVCMOS GND -1.65V±5% 3.3V C /3. ORE UTPUT OAD 1.25V± DDO LVCMOS GND -1.25V±5% 2.5V C /2. ...

Page 9

ICS8308I Data Sheet P ARAMETER DDO 0.8V Q0 DDO 0. 3.3V Q0: UTPUT ISE ALL ...

Page 10

ICS8308I Data Sheet IRING THE IFFERENTIAL NPUT TO Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V by the bias resistors R1 and R2. The bypass capacitor ...

Page 11

ICS8308I Data Sheet IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the V and V input requirements. Figures show ...

Page 12

ICS8308I Data Sheet S E CHEMATIC XAMPLE Figure 3 shows a schematic example of the ICS8308I. In this example, the LVCMOS_CLK input is selected. The decoupling VDD Ohm Ohm R11 43 3.3V_LVCMOS VDD=3.3V (U1,9) ...

Page 13

ICS8308I Data Sheet ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS8308I is: 1040 ...

Page 14

ICS8308I Data Sheet ABLE RDERING NFORMATION ...

Page 15

ICS8308I Data Sheet ...

Page 16

ICS8308I Data Sheet We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road Sales San Jose, CA 95138 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to ...

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