XC3S1600E-4FG320C Xilinx Inc, XC3S1600E-4FG320C Datasheet - Page 200
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XC3S1600E-4FG320C
Manufacturer Part Number
XC3S1600E-4FG320C
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin FBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-4FG320C
Package
320FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
250
Ram Bits
663552
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1600E-4FG320C
Manufacturer:
XILINX
Quantity:
142
Part Number:
XC3S1600E-4FG320C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Pinout Descriptions
User I/Os by Bank
Table
able user-I/O pins are distributed between the four I/O
banks on the FT256 package.
Table 144: User I/Os Per Bank on XC3S250E in the FT256 Package
Table 145: User I/Os Per Bank on XC3S500E in the FT256 Package
.
Table 146: User I/Os Per Bank on XC3S1200E in the FT256 Package
200
Notes:
1.
2.
Notes:
1.
2.
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
Package
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
Edge
Edge
144,
Table
145, and
I/O Bank
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
0
1
2
3
Table 146
Maximum
Maximum
Maximum
172
190
190
indicate how the avail-
I/O
I/O
I/O
44
42
44
42
46
48
48
48
46
48
48
48
I/O
I/O
I/O
20
10
24
62
22
15
11
28
76
24
14
13
27
78
8
www.xilinx.com
The XC3S250E FPGA in the FT256 package has 18 uncon-
nected balls, labeled with an “N.C.” type. These pins are
also indicated with the black diamond ( ) symbol in
Figure
INPUT
INPUT
INPUT
10
33
10
33
31
7
9
7
7
9
7
8
8
7
8
All Possible I/O Pins by Type
All Possible I/O Pins by Type
All Possible I/O Pins by Type
86.
DUAL
DUAL
DUAL
21
24
46
21
24
46
21
24
46
1
0
1
0
1
0
DS312-4 (v3.8) August 26, 2009
VREF
VREF
VREF
15
19
19
5
4
3
3
5
5
4
5
5
5
4
5
(1)
Product Specification
(1)
(1)
CLK
CLK
CLK
0
0
0
0
0
0
16
16
16
8
8
(2)
(2)
8
8
8
8
(2)
(2)
(2)
(2)
(1)
(1)
(1)
R
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