MAX512CSD+ Maxim Integrated Products, MAX512CSD+ Datasheet - Page 8
![IC DAC TRPL VOLT-OUT 8BIT 14SOIC](/photos/6/57/65727/175-14-soic_sml.jpg)
MAX512CSD+
Manufacturer Part Number
MAX512CSD+
Description
IC DAC TRPL VOLT-OUT 8BIT 14SOIC
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX512CPD.pdf
(16 pages)
Specifications of MAX512CSD+
Settling Time
70µs
Number Of Bits
8
Data Interface
Serial
Number Of Converters
3
Voltage Supply Source
Dual ±
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Number Of Dac Outputs
3
Resolution
8 bit
Interface Type
Serial (SPI)
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Maximum Power Dissipation
667 mW
Minimum Operating Temperature
0 C
Supply Current
1.3 mA
Voltage Reference
External
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power Dissipation (max)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
(T
8
_____________________________Typical Operating Characteristics (continued)
______________________________________________________________Pin Description
A
PIN
10
11
12
13
14
1
2
3
4
5
6
7
8
9
= +25°C, unless otherwise noted.)
_______________________________________________________________________________________
A: CS, 2V/div
B: OUTA, 1V/div
V
DAC LOADED WITH ALL 1s
DD
–
R
REFAB
—
NAME
OUTA
OUTB
OUTC
SCLK
REFC
LOUT
= 3V, V
GND
E
V
DIN
—
V
I.C.
–
C
—
S
DD
SS
—
S
–
TIME EXITING SHUTDOWN MODE
E
—
SS
T
–
= 0V, REFAB = V
Serial Data Input of the 16-bit shift register. Data is clocked into the register on the rising edge of SCLK.
Chip Select (active low). Enables data to be shifted into the 16-bit shift register. Programming commands
are executed at the rising edge of
Serial Clock Input. Data is clocked in on the rising edge of SCLK.
Asynchronous reset input (active low). Clears all registers to their default state (FFhex for DAC A and
DAC B registers); all other registers are reset to 0 (including the input shift register).
Positive Power Supply (2.7V to 5.5V). Bypass with 0.22µF to GND.
Ground
Negative Power Supply 0V or (-1.5V to -5.5V). Tie to GND for single supply operation. If a negative supply
is applied, bypass with 0.22µF to GND.
DAC A Output Voltage (Buffered). Resets to full scale. Connect 0.1µF capacitor or greater to GND.
DAC B Output Voltage (Buffered). Resets to full scale. Connect 0.01µF capacitor or greater to GND.
DAC C Output Voltage (Unbuffered). Resets to zero.
DAC C Reference Voltage
DAC A/B Reference Voltage
Internally connected. Do not make connections to this pin.
Logic Output (latched)
20 s/div
DD,
R
L
= 1k , C
L
= 0.1 F
A
B
–
C
—
S
–
.
FUNCTION
DIGITAL CODE = 80, REFAB = V
OUTPUT VOLTAGE NOISE DC TO 1MHz
2ms/div
DD,
NO LOAD
OUTA,
200 V/div