LE58QL063HVC Zarlink, LE58QL063HVC Datasheet - Page 64

• Manufacturer Part Number: LE58QL063HVC
• Description: SLIC 4-CH 3.3V 64-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of LE58QL063HVC

• Package: 64LQFP
• Number Of Channels Per Chip: 4
• Polarity Reversal: Yes
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

Upstream C/I Channel
The SC channel, which includes the six C/I channel bits, is transmitted upstream every frame. The bit definitions for the upstream
C/I channel are shown below. These bits are transmitted by the QLSLAC device (Most significant bit first).
GCI Format
|<----------------------- C/I FIELD ------------->|
Upstream Bit Definitions of the C/I field require the programmable I/O ports to be programmed as inputs. Otherwise, these bits
follow the downstream C/I bits for CD1
CDA
CDB
C3
In GCI mode, C4 and C5 are not available as upstream C/I data but can be obtained by reading the SLIC device I/O register.
Monitor Channel
The Monitor Channel (see Figure 28) is used to read and write the QLSLAC device’s coefficient registers, to read the status of
the device and the contents of the internal registers, and to provide supplementary signaling. Information is transferred on the
Monitor Channel using the MR and MX bits of the SC channel, providing a secure method of data exchange between the
upstream and downstream devices.
The Monitor byte is the third byte in the 4 byte GCI channel and is received every 125 µs over the DU or DD pins. A Monitor
command consists of one address byte, one or more command bytes, and is followed by additional bytes of input data as
required. The command may be followed by the QLSLAC device sending data bytes upstream via the DU pin.
Monitor Channel Protocol
<------------------------ Upstream SC Octet ------------------>
MSB
C3
C
7
An inactive (high) MX and MR pair bit for two or more consecutive frames shows an idle state on the monitor channel
and the end of message (EOM).
Transmitter
–C3
1
C
C
Receiver
: Debounced CD1
: The filtered CD2
C
CDB
of channel C.
6
1
MX
MX
MR
MR
CDA
5
1
C
C
C3
bit of channel x in non-E1 demultiplexed mode or the filtered CD1B
4
bit of channel x.
2
CDB
3
Figure 28. Maximum Speed Monitor Handshake Timing
1st Byte
2
C
CDA
, CD2
1st Byte
2
ACK
2
C
, and C3
MR
1
Zarlink Semiconductor Inc.
LSB
MX
125 µs
C
0
.
2nd Byte
64
2nd Byte
ACK
3rd Byte
3rd Byte
ACK
C
bit in the E1 demultiplexed mode.
EOM