PCI 9080-3 PLX Technology, PCI 9080-3 Datasheet - Page 2

• Manufacturer Part Number: PCI 9080-3
• Description: PCI Bus Master I/O Accelerator Chip 208-Pin PQFP
• Manufacturer: PLX Technology

Specifications of PCI 9080-3

• Package: 208PQFP

PLX Technology, Inc.
390 Potrero Ave.
Sunnyvale, CA 94086 USA
Tel: [phone]
Fax: [phone]
Email: [e-mail]
Web Site: www.plxtech.com
T E C H N O L O G Y
PCI 9080 Internal Block Diagram
9080-PB-010
®
P r o d u c t O r d e r i n g I n f o r m a t i o n
*See PLX web site for latest version and product support information
© 1998 by PLX Technology, Inc. All rights reserved. PLX and PLXMon 98 are trademarks of PLX Technology, Inc. which may be regis
product names that appear in this material are for identi cation purposes only and are acknowledged to be trademarks or regist
Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any
Technology reserves the right, without notice, to make changes in product design or speci cation.
T e c h n i c a l S p e c i c a t i o n s
P
P
I 2 O messaging unit
Interface protocol
P
Local bus speed
Big/Little Endian conversion
P
PCI host capability
Mailbox registers
Doorbell registers
Unaligned DMA transfer support
Programmable local bus modes
Serial EEPROM interface
P
I
P
2
c a
I C
I C
C
I C
C
O
B I
S I
a k
o c
i s
0 9
S
D
s u
n g
D
e g
m
0 8
K
K
i l a
i l p
S
e p
g n
n a
d e
e c
Interface
& Arbiter
PCI Bus
Control
Logic
Master Xfers)
PCI Initiator
Slave Xfers)
PCI Initiator
DMA Xfers)
PCI Initiator
DMA Xfers)
Machines
(For Direct
PCI Target
(for Direct
(For Ch 1
(For Ch 0
Mode C
Mode J
Mode S
PCI Bus
State
I
2
0 Messaging
Dir. Master Write
Dir. Master Read
P
I
Motorola MPC860 CPU, Intel i960 CPU, IBM PPC 401 CPU
P
Intel i960 CPU, IBM PPC 401 CPU
Dir. Slave Write
Dir. Slave Read
I
DMA1 PCI/Loc
DMA1 Loc/PCI
DMA0 PCI/Loc
DMA0 Loc/PCI
2
2
Local Con g
O Messaging
I C
C
Registers
PCI Con g
Run-Time
Internal
O Software Development Kit for
FIFOs
DMA
S I
DMA
o t
2
P
. 3
and the internal register accesses on the local side
3 3
Two 32-bit, one from PCI to local bus, one from local bus to PCI bus
f o
32-bit address/32-bit data, non multiplexed
32-bit address/32-bit data, multiplexed
32-bit address/16-bit data, non multiplexed
8 0
C
Eight 32-bit, accessed from PCI or local bus
0-40MHz
Type 0 or Type 1 PCI con guration cycles in direct master mode
PCI extension of the I
v 3
Supported
Direct bus master
o L
M
w t
l I
Dynamic switching for direct slave, direct master, DMA,
From any byte boundary
Selected through mode pins
p -
a c
c o
z H
r o
a
n i
e r
B l
l a
v 5
m
DMA Chaining
P
D
s u
u b
Q
x a
Initialization
Master Xfers)
Master Xfers)
Local Master
Local Master
Local Master
e
DMA Xfers)
DMA Xfers)
EEPROM
Local Bus
Machines
Local Slave
(for Direct
(for Direct
P F
(for Ch 1
(for Ch 0
e v
s s
State
M
o l
a
e p
t s
p
i c
m
r e
c i f
e
Unaligned Xfer
C
t n
i t a
h
2 O speci cation v.1.5
Local Bus
Interface
– Select Bus
– Endian
– Select Muxe
p i
i K
Width 8,16
or non-Muxe
Addr/Data
n o
or 32 bit
Conversion
f t
v ,
r o
2 .
M
1 .
o
o t
o r
a l
9/98 5K
ered trademarks of their respective companies.
errors that may appear in this material. PLX
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tered in some jurisdictions. All other
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