83947AYILN Integrated Device Technology (Idt), 83947AYILN Datasheet

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83947AYILN

Manufacturer Part Number
83947AYILN
Description
Clock Driver 2-IN LVCMOS/LVTTL 32-Pin TQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.83947AYILN.pdf (10 pages)

Specifications of 83947AYILN

Package
32TQFP
Configuration
1 x 2:1
Input Signal Type
LVCMOS|LVTTL
Maximum Output Frequency
110(Min) MHz
Operating Supply Voltage
3.3 V
G
The ICS83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer.
The low impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased from 9 to 18 byutilizing
the ability of the outputs to drive two series terminated lines.
Guaranteed output and part-to-part skew characteristics
make the ICS83947I ideal for high performance, single ended
applications that also require a limited output voltage.
CLK_SEL
83947AYI
B
CLK_EN
ENERAL
LOCK
CLK0
CLK1
OE
D
IAGRAM
D
0
1
ESCRIPTION
D
LE
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
www.idt.com
1
P
F
• 9 LVCMOS/LVTTL outputs
• Selectable CLK0 and CLK1 can accept the following
• Maximum output frequency: 110MHz
• Output skew: 500ps (maximum)
• Part-to-part skew: 2ns (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
input levels: LVCMOS and LVTTL
EATURES
IN
CLK_SEL
CLK_EN
A
CLK0
CLK1
GND
GND
V
SSIGNMENT
OE
DD
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
LVCMOS F
ICS83947I
32-Lead LQFP
Y Package
Top View
L
OW
ICS83947I
ANOUT
S
24
23
22
21
20
19
18
17
KEW
REV. B AUGUST 9, 2010
GND
Q3
V
Q4
GND
Q5
V
GND
DDO
DDO
, 1-
B
UFFER
TO
-9

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83947AYILN Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, θ JA Storage Temperature, T -65°C to 150°C STG T 4A ...

Page 4

ABLE HARACTERISTICS ...

Page 5

P ARAMETER 1.65V ± 0.15V V DD LVCMOS GND -1.65V ± 0.15V 3. UTPUT OAD EST IRCUIT PART 1 V DDO Qx 2 PART 2 V DDO sk(pp ...

Page 6

ABLE VS IR LOW ABLE FOR JA θ θ θ θ θ Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The ...

Page 7

ACKAGE UTLINE UFFIX FOR ABLE ...

Page 8

ABLE RDERING NFORMATION ...

Page 9

...

Page 10

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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