LFE2-12E-6QN208I Lattice, LFE2-12E-6QN208I Datasheet - Page 25

• Manufacturer Part Number: LFE2-12E-6QN208I
• Description: FPGA LatticeECP2 Family 12000 Cells 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Lattice

Specifications of LFE2-12E-6QN208I

• Package: 208PQFP
• Family Name: LatticeECP2
• Device Logic Units: 12000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 131
• Ram Bits: 226304
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
• MULT (Multiply)
• MAC (Multiply, Accumulate)
• MULTADDSUB (Multiply, Addition/Subtraction)
• MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available on each block depends in the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-7 shows the capabilities of the block.
Table 2-7. Maximum Number of Elements in a Block
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as a shift register from previous operand registers. By selecting “dynamic operation” the following opera-
tions are possible:
• In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.
• In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.
• The loading of operands can switch between parallel and serial operations.
MULT
MAC
MULTADDSUB
MULTADDSUBSUM
Width of Multiply
x9
8
2
4
2
2-22
x18
4
2
2
1
LatticeECP2/M Family Data Sheet
Architecture
x36
—
—
—
1