SI5010-B-GMR Silicon Laboratories Inc, SI5010-B-GMR Datasheet - Page 15

• Manufacturer Part Number: SI5010-B-GMR
• Description: Clock and Data Recovery 20-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5010-B-GMR

• Package: 20QFN EP
• Maximum Data Rate: 622.08 Mbps
• Power Supply Type: Analog
• Typical Supply Current: 124 mA
• Typical Operating Supply Voltage: 2.5 V
• Minimum Operating Supply Voltage: 2.375 V
• Maximum Operating Supply Voltage: 2.625 V

Pin #
12
13
15
16
17
19
20
PWRDN/CAL
CLKOUT–
CLKOUT+
Pin Name
RATESEL
DOUT+
DOUT–
NC
Table 8. Si5010 Pin Descriptions (Continued)
I/O
O
O
I
I
Signal Level
LVTTL
LVTTL
CML
CML
Rev. 1.4
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
Powerdown.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a
high-to-low transition on this pin. (See "4.2. PLL
Self-Calibration" on page 10.)
Note: This input has a weak internal pulldown.
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
Data Rate Select.
This pin configures the onboard PLL for clock and
data recovery at one of two user selectable data
rates. See Table 7 for configuration settings.
Note: This input has a weak internal pulldown.
No Connect.
This pin should be tied to ground.
Description
Si5010
15