LC51024MV-52F484C Lattice, LC51024MV-52F484C Datasheet - Page 63

• Manufacturer Part Number: LC51024MV-52F484C
• Manufacturer: Lattice

Lattice Semiconductor
ispXPLD 5512MX Logic Signal Connections (Continued)
1. Not available for differential pair.
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs.
sysIO
Bank
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVDS
100N
100P
101N
101P
102N
102P
103N
103P
104N
104P
105N
105P
106N
106P
107N
107P
108N
108P
Pair
96N
97N
98N
99N
96P
97P
98P
99P
—
—
—
—
Primary Macrocell/
GND (Bank 0)
GND (Bank 0)
Function
V
V
M12
M10
N30
N28
N26
N24
N22
N21
N20
N18
N16
N14
N12
N10
CCO0
CCO0
M8
M6
M5
M4
M2
M0
N8
N6
N5
N4
N2
N0
Macrocell 1 Macrocell 2
Alternate Outputs
M23
M22
M21
M20
M19
M18
O29
O28
O27
O26
O25
O24
O23
O22
O21
O20
O19
O18
O17
O16
O15
O14
O13
O12
M1
M0
—
—
—
—
63
O23
O22
O21
O20
O19
O18
O1
O0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Alternate
Input
M13
M11
N31
N29
N27
N25
N23
N19
N17
N15
N13
N11
M9
M7
M3
M1
N9
N7
N3
N1
—
—
—
—
—
—
—
—
—
—
ispXPLD 5000MX Family Data Sheet
Pin Number
208 PQFP
196
197
198
199
200
201
202
203
204
205
206
207
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GND (Bank 0) GND (Bank 0)
GND (Bank 0) GND (Bank 0)
Ball Number
256 fpBGA
V
V
CCO0
CCO0
B5
A3
B4
B3
C5
C6
D5
D6
A2
B2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Ball Number
484 fpBGA
V
V
A10
CCO0
CCO0
A9
C9
D9
E9
A8
B8
A7
B7
A5
B5
B6
C7
E8
E7
E6
D6
D8
D7
C6
C5
C4
D5
F9
F8
F7