SI5326C-C-GMR Silicon Laboratories Inc, SI5326C-C-GMR Datasheet - Page 58

• Manufacturer Part Number: SI5326C-C-GMR
• Manufacturer: Silicon Laboratories Inc

Si5326
7. Pin Descriptions: Si5326
58
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
2, 9, 14,
30, 33
Pin #
1
3
Pin Name
INT_C1B
RST
NC
I/O
—
O
I
INT_C1B
Signal Level
LVCMOS
LVCMOS
GND
VDD
RST
C2B
NC
XB
NC
XA
—
1
2
3
4
5
6
7
8
9
36
10 11 12 13 14 15 16 17
35
External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device reg-
isters to their default value. Clock outputs are tristated during reset.
The part must be programmed after a reset or power on to get a
clock output. See the Si53xx Family Reference Manual for details.
This pin has a weak pull-up.
No Connection.
Leave floating. Make no external connections to this pin for normal
operation.
Interrupt/CKIN1 Invalid Indicator.
This pin functions as a device interrupt output or an alarm output for
CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The
pin functions as a maskable interrupt output with active polarity con-
trolled by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS (and option-
ally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and
INT_PIN = 0.
0 = CKIN1 present
1 = LOS (FOS) on CKIN1
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
34
33
Rev. 1.0
GND
Pad
32
31
30
29
28
18
27
26
25
24
23
22
21
20
19
Description
SDI
A2_SS
A1
A0
SDA_SDO
SCL
CS_CA
INC
DEC