88PG8226A1-NFE1C000 Marvell, 88PG8226A1-NFE1C000 Datasheet - Page 47

• Manufacturer Part Number: 88PG8226A1-NFE1C000
• Manufacturer: Marvell

6
6.1
Copyright © 2008 Marvell
April 23, 2008, 2.00
Applications Information
PC Board Layout Considerations and Guidelines
The PC board layout is very critical in any switching converter. An improper layout can contribute to
system instability, excessive EMI (Electro-magnetic interference), and high switching loss. Follow
these basic guidelines for good PC layout:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Do not lay out the inductor first. The input capacitor placement is the most critical for proper
11. The 88PG82XX has two internal grounds, analog (SGND) and power (PGND). The analog
12. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as
13. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing
14. Try not to route analog or digital lines in close proximity to the power supply especially the VSW
This is a 2-layer board with 1 ground plane and 1 routing layer.
Copy the layout input
BOM in
Review the recommended solder pad layout and notes on
Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of
capacitor can be placed in parallel with the input capacitor as long as the Ceramic input
capacitor is placed next to the IC. If Tantalum input capacitor is used, it must be rated for
switching regulator applications and the operating voltage must be derated by 50%.
Any type of capacitor can be placed in parallel with the output capacitor.
Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors
as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide
the lowest noise and smallest foot print solution.
Use planes for the ground, input and output power to maintain good voltage filtering, and to
keep power losses low.
If there is not enough space for a power plane for the input supply, then the input supply trace
must be at least 3/8 inch wide.
If there is not enough space for a power plane for the output supplies, then place the output as
close to the load as possible with a trace at least 3/8 inch wide.
operation. The AC current circulating through the input capacitor and loop 1 (LP1) are square
wave with rise and fall times of 8 ns and slew rates as high as 300 A/µs (see
these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per
inch of PCB trace, VIND = L * di/dt. Therefore, the ceramic input capacitor (C2 and C5) must be
placed as close as possible to the PVIN and PGND pins with a short and wide trace as
possible. Also, the PVIN and PGND traces must be placed on the top layer. This will isolate the
fast AC currents from interfering with the analog ground plane.
ground ties to all the noise sensitive signals (PSET, VSET, and SVIN) while the power ground
ties to the higher current power paths. Noise on an analog ground can cause problems with the
IC’s internal control and bias signals. For this reason, separate analog and power ground traces
are recommended. The signal ground is connected to the power ground at one point, which is
the (-) terminal of the output capacitor.
close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as
shown in
capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle.
node. If this can’t be avoided, shield these lines with a power plane placed between the VSW
node and the signal lines.
Table
Figure
15. Contact the factory where substitutions are made.
48, is recommended for best results.
Document Classification: Proprietary Information
Figure 48
and
Figure 49
PC Board Layout Considerations and Guidelines
as much as possible and use the recommended
page
50.
Applications Information
Doc. No. MV-S103563-00 Rev. C
Figure
46). At
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