MAX5633UCB+D Maxim Integrated Products, MAX5633UCB+D Datasheet - Page 4

• Manufacturer Part Number: MAX5633UCB+D
• Description: IC DAC 16BIT 32CH S&H 64-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5633UCB+D

• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 32
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -

16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
CLKSEL = +5V, f
4
Note 1: The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The
Note 2: Gain is calculated from measurements
Note 3: Steady-state change in any output with an 8V change in an adjacent output.
Note 4: Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
Note 5: External clock mode with the external clock not toggling.
Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex.
Note 7: The sequencer runs at f
Note 8: V
Note 9: Guaranteed by gain-error test.
Note 10: The serial interface is inactive. V
Note 11: The serial interface is active. V
POWER SUPPLIES
Logic Supply Current
SCLK High to CS High Hold Time
DIN to SCLK High Setup Time
DIN to SCLK High Hold Time
RST to CS Low
Positive Supply Voltage
Negative Supply Voltage
Supply Difference
Logic Supply Voltage
Positive Supply Current
Negative Supply Current
DD
_______________________________________________________________________________________
= +10V, V
output voltage is limited by the Output Range specification, restricting the useable range of DAC codes. The nominal zero-
scale voltage may be achieved when V
for voltages V
for voltages V
for voltages V
for voltages V
updates. Tested with an external sequencer clock frequency of 480kHz.
limited by acceptable droop and update time after a Burst Mode Update.
PARAMETER
DD
rise to CS low = 500µs maximum.
SS
ECLK
= -4V, V
= 400kHz, T
DD
DD
DD
DD
= 10V and V
= 11.6V and V
= 9.25V and V
= 8.55V and V
LOGIC
SEQ
A
= V
= T
SYMBOL
V
V
= f
I
V
t
LDAC
LOGIC
LOGIC
SS
CSH1
LDAC
V
V
MIN
LSHA
t
t
I
I
IH
DH
DD
DS
SS
ECLK
DD
SS
SS
SS
SS
IH
= -4V at codes C000 hex and 4F2C hex,
= V
to T
= -2.9V at codes FFFF hex and 252E hex,
= -5.25V at codes D4F6 hex and 0 hex, and
= -2.75V at codes C74A hex and 281C hex.
,
= V
= V
,
/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
LOGIC
MAX
LOGIC
SS
(Note 8)
(Note 9)
(Note 9)
V
(Note 10)
f
LSHA
SCLK
DD
< -4.9V, and the nominal full-scale voltage may be achieved when V
, unless otherwise noted. Typical values are at T
, V
- V
, V
= +5V, V
= 20MHz (Note 11)
IL
SS
IL
= 0.
= 0.
(Note 9)
REF
CONDITIONS
= +2.5V, AGND = DGND = V
-5.25
8.55
4.75
MIN
15
GS
0
0
A
= +25°C.)
= 0, R
TYP
10
32
32
-4
5
1
2
L
≥ 10MΩ, C
-2.75
MAX
11.6
14.5
5.25
500
1.5
DD
42
40
3
> +11.5V.
L
= 50pF,
UNITS
mA
mA
mA
ns
ns
ns
µs
V
V
V
V