AD5300BRM-REEL7 Analog Devices Inc, AD5300BRM-REEL7 Datasheet
AD5300BRM-REEL7
Specifications of AD5300BRM-REEL7
Related parts for AD5300BRM-REEL7
AD5300BRM-REEL7 Summary of contents
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FEATURES Single 8-Bit DAC 6-Lead SOT-23 and 8-Lead MSOP Packages Micropower Operation: 140 Power-Down to 200 2 5.5 V Power Supply Guaranteed Monotonic by ...
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AD5300–SPECIFICATIONS Parameter 2 STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient 3 OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Digital-to-Analog Glitch Impulse ...
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... AD5300BRT-500RL7 AD5300BRT-REEL AD5300BRT-REEL7 AD5300BRTZ-500RL7 AD5300BRTZ-REEL AD5300BRTZ-REEL7 max–T )/θ AD5300BRM AD5300BRM-REEL AD5300BRM-REEL7 NOTES SOT-23 MSOP Pb-free part. –3– AD5300 unless otherwise noted.) MIN MAX Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time ...
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AD5300 V OUT GND V DD SOT-23 MSOP Pin No. Pin No. Mnemonic Function Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. OUT 2 8 GND Ground Reference Point for All Circuitry on the ...
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TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot ...
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AD5300–Typical Performance Characteristics 1 INL @ 3V 0.5 INL @ 5V 0 –0.5 –1 100 150 200 250 CODE Figure 2. Typical INL Plot 1 0.5 MAX INL MAX ...
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250 200 150 100 50 0 – 120 TEMPERATURE – C Figure 11. Supply Current vs. Temperature 800 600 400 200 ...
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AD5300 GENERAL DESCRIPTION D/A Section The AD5300 DAC is fabricated on a CMOS process. The archi- tecture consists of a string DAC followed by an output buffer amplifier. Since there is no reference input pin, the power supply (V ) ...
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SCLK SYNC DB15 DIN INVALID WRITE SEQUENCE: TH SYNC HIGH BEFORE 16 FALLING EDGE SYNC Interrupt In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated ...
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AD5300 AD5300 to 68HC11/68L11 Interface Figure 26 shows a serial interface between the AD5300 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5300, while the MOSI output drives the serial data line of the DAC. ...
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R1 = 10k V V OUT 0.1 F AD5300 3-WIRE SERIAL INTERFACE Figure 30. Bipolar Operation with the AD5300 Two 8-Bit AD5300s Together Make One 15-Bit DAC By using the configuration in Figure 31, it can ...
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AD5300 1.60 BSC 0.15 MAX Revision History Location 11/03—Data Sheet changed from REV REV. C. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . ...