AD5405YCP Analog Devices Inc, AD5405YCP Datasheet - Page 13
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AD5405YCP
Manufacturer Part Number
AD5405YCP
Description
IC DAC DUAL 12BIT MULT 40-LFCSP
Manufacturer
Analog Devices Inc
Datasheet
1.AD5405YCPZ.pdf
(24 pages)
Specifications of AD5405YCP
Rohs Status
RoHS non-compliant
Settling Time
80ns
Number Of Bits
12
Data Interface
Parallel
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
50µW
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
40-LFCSP
For Use With
EVAL-AD5405EB - BOARD EVAL FOR AD5405
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TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
Differential Nonlinearity
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating temper-
ature range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For this DAC, ideal maximum output is
V
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the I
loading all 0s to the DAC and measuring the I
Minimum current flows into the I
loaded with all 1s.
Output Capacitance
Capacitance from I
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For this device, it is specified with
a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is typically
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the I
on the following circuitry. This noise is digital feedthrough.
REF
− 1 LSB. The gain error of the DAC is adjustable to zero
OUT
1 or I
OUT
1 terminal, it can be measured by
OUT
2 to AGND.
OUT
OUT
2 line when the DAC is
pins and, subsequently,
OUT
1 current.
Rev. B | Page 13 of 24
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC I
loaded to the DAC.
Digital Crosstalk
The glitch impulse transferred to the outputs of a DAC in
response to a full-scale code change (all 0s to all 1s, or vice
versa) in the input register of another DAC. It is expressed in
nV-sec.
Analog Crosstalk
The glitch impulse transferred to the output of one DAC due to a
change in the output of another DAC. It is measured by loading
one of the input registers with a full-scale code change (all 0s to
all 1s, or vice versa) while keeping LDAC high and then pulsing
LDAC low and monitoring the output of the DAC whose digital
code has not changed. The area of the glitch is expressed in nV-sec.
Channel-to-Channel Isolation
The portion of input signal from a DAC’s reference input that
appears at the output of the other DAC. It is expressed in decibels.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to the fifth harmonics.
Intermodulation Distortion (IMD)
The DAC is driven by two combined sine wave references
of frequencies fa and fb. Distortion products are produced
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3 ... Intermodulation terms are those for which m or n is
not equal to 0. The second-order terms include (fa + fb) and
(fa − fb), and the third-order terms are (2fa + fb), (2fa − fb),
(f + 2fa + 2fb), and (fa − 2fb). IMD is defined as
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
THD
IMD
=
=
20
20
log
log
(
rms
V
2
2
sum
+
rms
V
of
3
2
V
amplitude
+
1
the
V
OUT
4
sum
2
1 terminal when all 0s are
+
V
and
5
of
2
the
diff
fundamenta
distortion
AD5405
products
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)