AD9786BSV Analog Devices Inc, AD9786BSV Datasheet
AD9786BSV
Specifications of AD9786BSV
Available stocks
Related parts for AD9786BSV
AD9786BSV Summary of contents
Page 1
FEATURES 16-bit resolution, 200 MSPS input data rate IMD 90 dBc @10 MHz Noise spectral density (NSD): −164 dBm/ MHz WCDMA ACLR = 80 dBc @ 40 MHz IF DNL = ±0.3 LSB INL = ±0.6 LSB Selectable ...
Page 2
AD9786 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 DC Specifications ......................................................................... 5 Dynamic Specifications ............................................................... 6 Digital Specifications ................................................................... 7 ...
Page 3
REVISION HISTORY 10/05—Rev Rev. B Updated Format.................................................................. Universal Changes to Figure 1...........................................................................1 Changes to Table 2 ............................................................................6 Changes to Table 3 ............................................................................7 Changes to External Sync Mode Section .....................................31 Updated Outline Dimensions........................................................58 Changes to Ordering Guide...........................................................58 2/05—Rev. 0 ...
Page 4
AD9786 GENERAL DESCRIPTION The AD9786 is a 16-bit, high speed, CMOS DAC with 2×/4×/8× interpolation and signal processing features tuned for communications applications. It offers state-of-the-art distortion and noise performance. The AD9786 was developed to meet the demanding performance requirements ...
Page 5
SPECIFICATIONS DC SPECIFICATIONS AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2 MIN MAX Table 1. Parameter RESOLUTION 1 DC Accuracy Integral Nonlinearity Differential Nonlinearity ANALOG OUTPUT Offset Error Gain Error ...
Page 6
AD9786 DYNAMIC SPECIFICATIONS AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2 MIN MAX coupled output; 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Minimum DAC Output ...
Page 7
DIGITAL SPECIFICATIONS AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input ...
Page 8
AD9786 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter With Respect to AVDD1, AVDD2, AGND1, AGND2, DRVDD ACGND, ADGND, CLKGND, DGND ACVDD, ADVDD, AGND1, AGND2, CLKVDD, DVDD ACGND, ADGND, CLKGND, DGND AGND1, AGND2, AGND1, AGND2, ACGND, ADGND, ACGND, ADGND, CLKGND, DGND CLKGND, ...
Page 9
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLKVDD CLKVDD CLKGND CLKGND DNC = DO NOT CONNECT CLOCK Table 6. Clock Pin Function Descriptions Pin No. Mnemonic Direction 5, 6 CLK+, CLK– DNC 31 DATACLK I CLKVDD 4, 7 ...
Page 10
AD9786 ANALOG Table 7. Analog Pin Function Descriptions Pin No. Mnemonic 59 REFIO 60 FSADJ 70, 71 IOUTB, IOUTA 61 DNC 62, 79 ADVDD 63, 78 ADGND 64, 77 ACVDD 65, 76 ACGND 66, 75 AVDD2 67, 74 AGND2 68, ...
Page 11
SERIAL INTERFACE Table 9. Serial Interface Pin Function Descriptions Pin No. Mnemonic Direction 54 SDO O 55 SDIO I/O 56 SCLK I 57 CSB I 58 RESET I Description SDIODIR CSB 0x00[7] Mode 1 X High impedance Serial ...
Page 12
AD9786 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL ...
Page 13
Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range Impulse Response Response of the device to an ...
Page 14
AD9786 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2 MIN MAX coupled output; 50 Ω doubly terminated, unless otherwise noted. 120 100 –6dBFS 80 60 0dBFS 40 ...
Page 15
F (MHz) OUT Figure 9. Out-of-Band SFDR 200 MSPS, 2× Interpolation DATA 100 95 0dBFS 90 85 –6dBFS 80 75 ...
Page 16
AD9786 100 95 –3dBFS 0dBFS 100 F (MHz) OUT Figure 15. Third-Order IMD vs. Frequency, f DATA 100 95 –3dBFS 90 –6dBFS ...
Page 17
F (MHz) OUT Figure 21. Third-Order IMD vs. Frequency 62.5 MSPS, 8× Interpolation DATA 1.25 1.00 ...
Page 18
AD9786 –150 –152 –154 A = –3dBFS IN –156 –158 A = 0dBFS IN –160 –162 A IN –164 –166 –168 –170 100 ANALOG OUTPUT FREQUENCY (MHz) Figure 27. Noise Spectral Density vs. Analog Input ...
Page 19
REF –22.76dBm *ATTEN 8dB *AVG Log 10dB/ AVERAGE 22 PAVG CENTER 20.00MHz *RES BW 30kHz VBW 300kHz SWEEP 109.8ms (601 pts) LOWER RMS RESULTS FREQ OFFSET REF BW dBc dBm CARRIER POWER 5.000MHz 3.840MHz –79.00 –89.38 –10.38dBm/ ...
Page 20
AD9786 SERIAL CONTROL INTERFACE SDO (PIN 54) SDIO (PIN 55) AD9786 SPI SCLK (PIN 56) PORT INTERFACE CSB (PIN 57) Figure 36. AD9786 SPI Port Interface The AD9786 serial port is a flexible, synchronous serial commu- nications port, allowing easy ...
Page 21
MSB/LSB TRANSFERS The AD9786 serial port can support both MSB-first or LSB-first data formats. This functionality is controlled by register address DATADIR (0x00[6]). The default is MSB first. When this bit is set active high, the AD9786 serial port is ...
Page 22
AD9786 MODE CONTROL (VIA SERIAL PORT) Table 11. Address Bit 7 Bit 6 COMMS 00 SDIODIR DATADIR FILTER 01 INTERP[1] INTERP[0] DATA 02 DATAFMT ONEPORT MODULATE 03 CHANNEL HILBERT RESERVED 04 Reserved Reserved DCLKCRC 05 DATAADJ[3] DATAADJ[ ...
Page 23
Table 14. DATA(02) Bit Direction DATAFMT 7 I ONEPORT 6 I DCLKSTR 5 I DCLKPOL 4 I DCLKEXT 3 I DCLKCRC 2 I IQPOL 1 I GRAYDIN 0 I Table 15. MODULATE(03) Bit Direction CHANNEL 7 I HILBERT 6 I ...
Page 24
AD9786 Table 16. DCLKCRC(05) Bit Direction DATAADJ[3:0] [7:4] I MODSYNC 3 I MODADJ[2:0] [2:0] I Table 17. VERSION(0D) Bit Direction VERSION[3:0] [3:0] O Table 18. CALMEMCK(OE) Bit Direction CALMEM [5:4] O CALCKDIV[2:0] [2:0] I Table 19. MEMRDWR(OF) Bit Direction CALSTAT ...
Page 25
Table 20. MEMADDR(10) Bit Direction MEMADDR [7:0] [7:0] I/O Table 21. MEMDATA(11) Bit Direction MEMDATA [5:0] [5:0] I/O Table 22. DCRCSTAT(12) Bit Direction DCRCSTAT ( DCRCSTAT( DCRCSTAT( Default Description 00000000 Address of factory or ...
Page 26
AD9786 DIGITAL FILTER SPECIFICATIONS DIGITAL INTERPOLATION FILTER COEFFICIENTS Table 23. Stage 1 Interpolation Filter Coefficients Lower Coefficient Upper Coefficient H(1) H(43) H(2) H(42) H(3) H(41) H(4) H(40) H(5) H(39) H(6) H(38) H(7) H(37) H(8) H(36) H(9) H(35) H(10) H(34) H(11) ...
Page 27
CLOCK/DATA TIMING Table 26. Data Port Synchronization DCLKEXT MODSYNC 0x02, Bit 3 0x05, Bit Two-Port Data Input Mode (DATACLK Master) With the interpolation set to 1×, the ...
Page 28
AD9786 Figure 46. DATACLK Duty Cycle t = 6ns TYP –0.5ns MIN S Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 5ns TYP –0.5ns MIN = 2.9ns MIN S ...
Page 29
Low Setup/Hold Mode (DATACLK Input, Data Recovery Off) Some applications might require that digital input data be synchronized with the DATACLK input, rather than DACCLK. For these applications, the AD9786 can be programmed for low setup/hold mode by entering the ...
Page 30
AD9786 Note that the data in Figure 44 to Figure 53 was taken with the DATAADJ default of 0000. Changing the DATAADJ values allows the user to select the specific edge of DACCLK upon which the input data is latched. ...
Page 31
Interpolation Modes Table 28. Interpolation Modes INTERP[1] INTERP[0] Mode interpolation 0 1 ×2 interpolation 1 0 ×4 interpolation 1 1 ×8 interpolation Interpolation is the process of increasing the number of points in a time domain waveform ...
Page 32
AD9786 REAL AND COMPLEX SIGNALS A complex signal contains both magnitude and phase information. Given two signals at the same frequency, if the leading signal in phase is cosinusoidal and the lagging signal is sinusoidal, information pertaining to the magnitude ...
Page 33
MODULATION MODES Table 30. Single-Channel Modulation MODDUAL CHANNEL Either channel of the AD9786 interpolation filter channels can be routed to the DAC and modulated. ...
Page 34
AD9786 0 –50 –100 –150 –8 –6 –4 0 –50 –100 –150 –8 –6 –4 0 –50 –100 –150 –8 –6 –4 0 –50 –100 –150 –8 –6 –4 FILTERED INTERPOLATION IMAGES f /8 MODULATION S Figure 59. Double Sideband ...
Page 35
Figure 61. Real Modulation –50 –100 –150 –8 ...
Page 36
AD9786 Table 33. Dual-Channel Complex Modulation MODDUAL CHANNEL dual-channel mode, the two channels can be modulated by a complex signal, with either the ...
Page 37
Figure 64. Complex Modulation –50 –100 –150 –8 –6 –4 0 –50 –100 –150 –8 –6 ...
Page 38
AD9786 POWER DISSIPATION The AD9786 has seven power-supply domains: two 3.3 V analog domains (AVDD1 and AVDD2), two 2.5 V analog domains (ADVDD and ACVDD), one 2.5 V clock domain (CLKVDD), and two digital domains (DVDD, which runs from 2.5 ...
Page 39
Table 35. Dual Channel Complex Modulation with Hilbert Hilbert Mode 0 Hilbert transform off 1 Hilbert transform on When complex modulation is performed, the entire spectrum is translated by the modulation factor. If the resulting modulated spectrum is not mirrored ...
Page 40
AD9786 Figure 72 shows this effect at the DAC output for a signal mirrored asymmetrically about dc that is produced by complex modulation without a Hilbert transform. The signal bandwidth was narrowed to show the aliased negative frequency interpolation images. ...
Page 41
Figure 76. Phase Response of Hilbert Transform Table 37. Dual Channel Complex Modulation Sideband Selection Sideband Mode 0 Upper IF sideband rejected 1 Lower IF sideband rejected ...
Page 42
AD9786 Master/Slave, Modulator/DATACLK Master Modes In applications where two or more AD9786s are used to synthe- size several digital data paths, it might be necessary to ensure that the digital inputs to each device are latched synchronously. In complex data ...
Page 43
DATADJ[3:0] 0000 DAC CLOCK RECEIVED CHANNEL DATA RATE CLOCK LOCAL CHANNEL DATA RATE CLOCK Figure 82. Local Channel Data Rate Clock Synchronized with Offset STATE DECODE fs fs/4 0 fs/2 0 ...
Page 44
AD9786 OPERATING THE AD9786 REV. F EVALUATION BOARD This section provides information to power up the board and verify correct operation; a description of more advanced modes of operation has been omitted. POWER SUPPLIES The AD9786 Rev. F evaluation board ...
Page 45
DATA INPUTS Digital data inputs to the AD9786 are accessed on the evaluation board through Connector J1 and Connector J2. These are 40-pin, right-angle connectors that are intended to be used with standard ribbon cable connectors. The input level should ...
Page 46
AD9786 Figure 87. Power Supply Distribution, Rev. F Evaluation Board Rev Page ...
Page 47
ADTL1-12 Figure 88. AD9786 Local Circuitry, Rev. F Evaluation Board Rev Page AD9786 ...
Page 48
AD9786 AX15 AX14 AX13 AX12 DATA-A AX15 2 1 AX14 4 3 AX13 6 5 AX12 8 7 AX11 10 9 AX10 12 11 AX09 14 13 AX08 16 15 AX07 18 17 AX06 20 19 AX05 22 21 AX04 ...
Page 49
R62 R57 100 Ω 100 Ω BX15 BX08 R58 100 Ω R61 BX09 100 Ω R59 BX14 100 Ω R60 BX10 100 Ω R63 BX13 100 Ω R64 BX11 100 Ω BX12 ...
Page 50
AD9786 DVDDS 4 PRE OPCLK_3 OPCLK 1 CLK CLR 15 74LCX112 DGND;8 U7 DVDDS;16 10 PRE CLK CLR 14 74LCX112 DGND;8 U7 DVDDS;16 ...
Page 51
Figure 92. PCB Assembly, Primary Side, Rev. F Evaluation Board Figure 93. PCB Assembly, Secondary Side, Rev. F Evaluation Board Rev Page AD9786 ...
Page 52
AD9786 Figure 94. PCB Assembly, Layer 1 Metal, Rev. F Evaluation Board Figure 95. PCB Assembly, Layer 6 Metal, Rev. F Evaluation Board Rev Page ...
Page 53
Figure 96. PCB Assembly, Layer 2 Metal (Ground Plane),Rev. F Evaluation Board Figure 97. PCB Assembly, Layer 3 Metal (Power Plane),Rev. F Evaluation Board Rev Page AD9786 ...
Page 54
AD9786 Figure 98. PCB Assembly, Layer 4 Metal (Power Plane), Rev. F Evaluation Board Figure 99. PCB Assembly, Layer 5 Metal (Ground Plane), Rev. F Evaluation Board Rev Page ...
Page 55
... COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range AD9786BSV −40°C to +85°C AD9786BSVRL −40°C to +85°C 1 AD9786BSVZ −40°C to +85°C 1 AD9786BSVZRL −40°C to +85°C AD9786- Pb-free part. 14.20 14.00 SQ 12.20 13.80 1.20 12.00 SQ MAX 11.80 80 ...
Page 56
AD9786 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03152-0-10/05(B) Rev Page ...