AD5453YUJ-REEL Analog Devices Inc, AD5453YUJ-REEL Datasheet - Page 5

• Manufacturer Part Number: AD5453YUJ-REEL
• Description: IC DAC 14BIT MULT TSOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD5453YUJ-REEL

• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055)
• Settling Time: 180ns
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TSOT-23-8, TSOT-8
• For Use With: EVAL-AD5453EB - BOARD EVAL FOR AD5453
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIMING CHARACTERISTICS
All input signals are specified with t
V
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
Update Rate
1
SCLK
1
2
3
4
5
6
7
8
Guaranteed by design and characterization, not subject to production test.
REF
= 10 V, temperature range for Y version: −40°C to +125°C. All specifications T
SYNC
SCLK
DIN
1
t
8
V
50
20
8
8
8
5
4.5
5
30
2.7
DD
= 2.5 V to 5.5 V
DB15
t
R
5
= t
t
6
F
= 1 ns (10% to 90% of V
t
2
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Unit
Figure 2. Timing Diagram
Rev. B | Page 5 of 28
t
1
t
3
DD
) and timed from a voltage level of (V
DB0
t
7
Conditions/Comments
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
MIN
AD5450/AD5451/AD5452/AD5453
to T
MAX
, unless otherwise noted.
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,