ATF1508ASL-20AC100 Atmel, ATF1508ASL-20AC100 Datasheet - Page 19

• Manufacturer Part Number: ATF1508ASL-20AC100
• Description: IC CPLD 128 MACROCELL LP 100TQFP
• Manufacturer: Atmel
• Series: ATF1508AS(L)r

Specifications of ATF1508ASL-20AC100

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 20.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Macrocells: 128
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 5V
• Memory Type: EEPROM
• Family Name: ATF1508ASL
• # Macrocells: 128
• Number Of Usable Gates: 3000
• Frequency (max): 41.7MHz
• Propagation Delay Time: 20ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 80
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: ATF1508ASL20AC100

AC Characteristics
0784P–PLD–7/05
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
t
t
t
t
t
t
t
t
t
PD1
PD2
SU
H
FSU
FH
COP
CH
CL
ASU
AH
ACOP
ACH
ACL
CNT
CNT
ACNT
ACNT
MAX
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
Parameter
Input or Feedback to
Non-registered Output
I/O Input or Feedback to
Non-registered Feedback
Global Clock Setup Time
Global Clock Hold Time
Global Clock Setup Time of
Fast Input
Global Clock Hold Time of
Fast Input
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
Array Clock Output Delay
Array Clock High Time
Array Clock Low Time
Minimum Clock Global Period
Maximum Internal Global
Clock Frequency
Minimum Array Clock Period
Maximum Internal Array
Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
Logic Control Delay
Internal Output Enable Delay
Output Buffer and Pad Delay
(Slow slew rate = OFF;
V
CCIO
= 5V; C
L
= 35 pF)
(1)
166.7
Min
125
125
0.5
6
0
3
3
3
3
2
3
3
-7
Max
7.5
4.5
7.5
0.5
0.5
0.8
7
8
8
1
4
3
3
2
2
Min
100
100
125
0.5
7
0
3
4
4
3
3
4
4
-10
Max
0.5
0.5
0.8
1.5
10
10
10
10
9
5
1
5
5
5
2
76.9
76.9
Min
100
1.0
11
3
3
0
3
5
5
4
4
6
6
-15
Max
15
12
15
13
13
8
2
2
2
8
1
6
6
3
4
41.7
Min
1.5
16
66
66
3
8
8
0
6
6
4
5
-20
Max
ATF1508AS(L)
20
20
16
10
17
17
10
2
2
2
1
7
7
3
5
33.3
Min
20
10
10
50
50
0
3
2
7
7
5
6
-25
Max
1.2
25
20
13
25
22
22
12
2
2
2
8
8
4
6
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19