EPM7128AETC100-10 Altera, EPM7128AETC100-10 Datasheet - Page 35
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EPM7128AETC100-10
Manufacturer Part Number
EPM7128AETC100-10
Description
IC MAX 7000 CPLD 128 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7128AETC100-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-1202
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128AETC100-10
Manufacturer:
ALTERA
Quantity:
32
Company:
Part Number:
EPM7128AETC100-10
Manufacturer:
ALTERA
Quantity:
33
Part Number:
EPM7128AETC100-10
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA
Quantity:
1 920
Company:
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA74
Quantity:
350
Part Number:
EPM7128AETC100-10N
Manufacturer:
ALTERA
Quantity:
20 000
Part Number:
EPM7128AETC100-10T
Manufacturer:
ALTERA
Quantity:
20 000
Altera Corporation
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
Table 18. EPM7032AE Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
Conditions
MAX 7000A Programmable Logic Device Data Sheet
Min
1.3
0.6
1.0
1.5
-4
Max
0.7
0.7
2.3
1.9
0.5
1.5
0.6
0.0
0.8
1.3
5.8
4.0
4.5
9.0
4.0
0.7
0.6
Note (1)
Speed Grade
Min
2.0
1.0
1.5
1.5
-7
Max
1.2
1.2
2.8
3.1
0.8
2.5
1.0
0.0
1.3
1.8
6.3
4.0
4.5
9.0
4.0
1.2
1.0
Min
2.8
1.3
1.5
1.5
-10
Max
10.0
1.2
1.5
1.5
3.4
4.0
1.0
3.3
0.0
1.8
2.3
6.8
5.0
5.5
5.0
1.5
1.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35