XC9572XL-10TQG100C Xilinx Inc, XC9572XL-10TQG100C Datasheet - Page 5

IC CPLD 1.6K 72MCELL 100-TQFP

XC9572XL-10TQG100C

Manufacturer Part Number
XC9572XL-10TQG100C
Description
IC CPLD 1.6K 72MCELL 100-TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr

Specifications of XC9572XL-10TQG100C

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
72
Number Of Gates
1600
Number Of I /o
72
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
FLASH
Cpld Type
FLASH
No. Of Macrocells
72
No. Of I/o's
72
Propagation Delay
10ns
Global Clock Setup Time
6.5ns
Frequency
100MHz
Supply Voltage Range
3V To 3.6V
Operating
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1512 - KIT DESIGN CPLD W/BATT HOLDER
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1386

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All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
DS054 (v2.5) May 22, 2009
Product Specification
54
R
Figure
4, the macrocell register clock
Figure 3: XC9500XL Macrocell Within Function Block
Allocator
Product
Term
Additional
Product
Terms
(from other
macrocells)
Additional
Product
Terms
(from other
macrocells)
Product Term Clock Enable
Product Term Clock
Product Term Reset
Product Term Set
Product Term OE
1
0
www.xilinx.com
Set/Reset
Global
XC9500XL High-Performance CPLD Family Data Sheet
Clocks
3
Global
CE
D/T
R
S
Q
OUT
PTOE
To
FastCONNECTII
Switch Matrix
DS054_03_042101
To
I/O Blocks
5

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