XC2C128-7VQG100C Xilinx Inc, XC2C128-7VQG100C Datasheet - Page 2
![IC CR-II CPLD 128MCELL 100-VQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XC2C128-7VQG100C
Manufacturer Part Number
XC2C128-7VQG100C
Description
IC CR-II CPLD 128MCELL 100-VQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C128-7VQG100C
Operating Temperature
0°C ~ 70°C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
3000
Number Of I /o
80
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
No. Of Macrocells
128
No. Of I/o's
80
Propagation Delay
5.7ns
Global Clock Setup Time
3ns
Frequency
244MHz
Supply Voltage Range
1.7V To 1.9V
Case
TQFP100
Dc
05+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1285
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C128-7VQG100C
Manufacturer:
XILINX
Quantity:
1 000
Company:
Part Number:
XC2C128-7VQG100C
Manufacturer:
XILINX
Quantity:
450
Part Number:
XC2C128-7VQG100C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC2C128 CoolRunner-II CPLD
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 128
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 128 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital technology, a design technique that makes use
of CMOS technology in both the fabrication and design
methodology. RealDigital technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high-perfor-
mance and low power operation.
Supported I/O Standards
The CoolRunner-II 128 macrocell features LVCMOS,
LVTTL, SSTL and HSTL I/O implementations. See
Table 2: I
2
Notes:
1.
Typical I
16-bit up/down, Resetable binary counter (one counter per function block).
CC
CC
(mA)
vs Frequency (LVCMOS 1.8V T
40
20
0
0.019
0
0
3.97
25
50
Table
7.95
A
Figure 1: I
50
= 25°C)
1). This
Table 1
www.xilinx.com
11.92
Frequency (MHz)
100
75
(1)
CC
Frequency (MHz)
vs Frequency
15.89
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL make use of a V
compliance. CoolRunner-II CPLDs are also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C128
(1) For information on assigning Vref pins, see
(2) LVCMOS15 requires use of Schmitt-trigger inputs.
100
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_1
SSTL2_1
SSTL3_1
IOSTANDARD
Attribute
150
23.83
150
(2)
27.80
175
Output
V
CCIO
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
200
31.93
DS093_041905
200
V
Input
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
DS093 (v3.2) March 8, 2007
35.73
250
225
Input
V
0.75
1.25
Product Specification
(1)
N/A
N/A
N/A
N/A
N/A
1.5
REF
REF
XAPP399
39.70
250
pin for JEDEC
Termination
Voltage V
Board
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
TT
R