XC95144XL-10TQG100I Xilinx Inc, XC95144XL-10TQG100I Datasheet - Page 15

• Manufacturer Part Number: XC95144XL-10TQG100I
• Description: IC CPLD 3.2K 144MCELL 100-TQFP
• Manufacturer: Xilinx Inc
• Series: XC9500XLr

Specifications of XC95144XL-10TQG100I

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 144
• Number Of Gates: 3200
• Number Of I /o: 81
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: FLASH
• Package: 100TQFP
• Family Name: XC9500XL
• Device System Gates: 3200
• Number Of Macro Cells: 144
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 81
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 90
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 122-1373

Detailed timing information may be derived from the full tim-
ing model shown in
DS054 (v2.5) May 22, 2009
Product Specification
T
PSU
R
Setup Time = T
T
T
T
Propagation Delay = T
T
GCK
GSR
GTS
IN
Figure
Combinatorial
P-Term Clock
Combinatorial
Logic
Logic
Path
(a)
16. The values and explanations
PSU
(c)
T
T
T
T
T
LOGILP
PD
Clock to Out Time = T
PTCK
PTSR
PTTS
LOGI
D/T Q
Figure 16: Detailed Timing Model
Figure 15: Basic Timing Model
S*T
T
PTA
www.xilinx.com
PCO
PCO
D/T
CE
for each parameter are given in the individual device data
sheets.
XC9500XL High-Performance CPLD Family Data Sheet
T
T
SUI
HI
T
T
T
SR
T
PDI
AOI
RAI
F
T
Macrocell
COI
Q
Setup Time = T
Internal System Cycle Time = T
Combinatorial
Combinatorial
Logic
Logic
T
SU
OUT
(b)
(d)
Clock to Out Time = T
D/T Q
T
D/T Q
SLEW
SYSTEM
DS054_15_042101
DS054_16_042101
T
CO
T
EN
CO
15