XC2C256-7VQG100C Xilinx Inc, XC2C256-7VQG100C Datasheet - Page 7

• Manufacturer Part Number: XC2C256-7VQG100C
• Description: IC CR-II CPLD 256MCELL 100-VQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C256-7VQG100C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 6000
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• No. Of Macrocells: 256
• No. Of I/o's: 80
• Propagation Delay: 5.7ns
• Global Clock Setup Time: 3.3ns
• Frequency: 152MHz
• Supply Voltage Range: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1573 - KIT STARTER COOLRUNNER-II LP/LC122-1512 - KIT DESIGN CPLD W/BATT HOLDER
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1402

DS094 (v3.2) March 8, 2007
Product Specification
Notes:
1.
2.
3.
4.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
AO
APRPW
PSU1
PSU2
PHD
PH
PCO
OE
POE
MOE
PAO
SUEC
HEC
CW
PCW
DGSU
DGH
DGR
DGW
CDRSU
CDRH
CONFIG
F
information).
F
macrocell while F
F
Typical configuration current during T
Symbol
/T
TOGGLE
SYSTEM1
EXT1
/T
/T
OD
POD
MOD
(4)
(1/T
R
is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more
(1/T
SU1
+T
CYCLE
P-term clock setup time (single p-term)
P-term clock setup time (OR array)
Direct input register p-term clock hold time
P-term clock hold
P-term clock to output
Global OE to output enable/disable
P-term OE to output enable/disable
Macrocell driven OE to output enable/disable
P-term set/reset to output valid
Global set/reset to output valid
Register clock enable setup time
Register clock enable hold time
Global clock pulse width High or Low
P-term pulse width High or Low
Asynchronous preset/reset pulse width (High or Low)
Set-up before DataGATE latch assertion
Hold to DataGATE latch assertion
DataGATE recovery to new data
DataGATE low pulse width
CDRST setup time before falling edge GCLK2
Hold time CDRST after falling edge GCLK2
Configuration time
CO
SYSTEM2
) is the maximum external frequency using one p-term while F
) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per
is through the OR array.
CONFIG
Parameter
is approximately 7.7
www.xilinx.com
m
A.
EXT2
is through the OR array.
Min.
1.2
1.5
1.1
1.0
2.8
1.1
6.0
6.0
4.0
2.5
1.6
0
0
0
-
-
-
-
-
-
-
-
-6
XC2C256 CoolRunner-II CPLD
Max.
150
6.5
5.6
7.3
7.4
7.5
5.7
8.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min.
1.5
2.0
1.2
1.0
3.1
1.6
7.5
7.5
6.0
3.5
2.0
0
0
0
-
-
-
-
-
-
-
-
-7
Max.
150
7.3
7.0
8.0
9.9
8.1
7.6
9.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
7