EPM570F100I5N Altera, EPM570F100I5N Datasheet - Page 26
![IC MAX II CPLD 570 LE 100-FBGA](/photos/6/71/67105/544-100-fbga_sml.jpg)
EPM570F100I5N
Manufacturer Part Number
EPM570F100I5N
Description
IC MAX II CPLD 570 LE 100-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570F100I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
76
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
100-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
No. Of I/o's
76
Propagation Delay
8.7ns
Global Clock Setup Time
1.9ns
Frequency
201.1MHz
Supply Voltage Range
2.375V To 2.625V, 3V To 3.6V
Operating Temperature Range
-40°C To +100°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1717
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570F100I5N
Manufacturer:
ALTERA
Quantity:
319
Part Number:
EPM570F100I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–18
Figure 2–14. Global Clock Network
Notes to
(1) LAB column clocks in I/O block regions provide high fan-out output enable signals.
(2) LAB column clocks drive to the UFM block.
User Flash Memory Block
MAX II Device Handbook
I/O Block Region
LAB Column
Figure
clock[3..0]
2–14:
I/O Block Region
MAX II devices feature a single UFM block, which can be used like a serial EEPROM
for storing non-volatile information up to 8,192 bits. The UFM block connects to the
logic array through the MultiTrack interconnect, allowing any LE to interface to the
UFM block.
used to create customer interface or protocol logic to interface the UFM block data
outside of the device. The UFM block offers the following features:
■
■
■
■
4
Non-volatile storage up to 16-bit wide and 8,192 total bits
Two sectors for partitioned sector erase
Built-in internal oscillator that optionally drives logic array
Program, erase, and busy signals
4
(Note 1)
Figure 2–15
4
4
shows the UFM block and interface signals. The logic array is
4
CFM Block
UFM Block (2)
4
4
I/O Block Region
4
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
User Flash Memory Block
LAB Column
clock[3..0]