EPM570F256C4N Altera, EPM570F256C4N Datasheet - Page 36
![IC MAX II CPLD 570 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM570F256C4N
Manufacturer Part Number
EPM570F256C4N
Description
IC MAX II CPLD 570 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570F256C4N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
160
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
No. Of I/o's
160
Propagation Delay
7ns
Global Clock Setup Time
1.5ns
Frequency
247.5MHz
Supply Voltage Range
2.375V To 2.625V, 3V To 3.6V
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
No. Of Macrocells
440
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1313
EPM570F256C4N
EPM570F256C4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570F256C4N
Manufacturer:
ALTERA
Quantity:
50
Part Number:
EPM570F256C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–28
Figure 2–23. MAX II I/O Banks for EPM1270 and EPM2210
Notes to
(1)
(2)
MAX II Device Handbook
Figure 2–23
Figure 2–23
Figure
2–23:
is a top view of the silicon die.
is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.
I/O Bank 1
Each I/O bank has dedicated V
in that bank. A single device can support 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each
individual bank can support a different standard. Each I/O bank can support
multiple standards with the same V
V
the input and output buffers in MAX II devices.
The JTAG pins for MAX II devices are dedicated pins that cannot be used as regular
I/O pins. The pins TMS, TDI, TDO, and TCK support all the I/O standards shown in
Table 2–4 on page 2–27
devices and their I/O standard support is controlled by the V
PCI Compliance
The MAX II EPM1270 and EPM2210 devices are compliant with PCI applications as
well as all 3.3-V electrical specifications in the PCI Local Bus Specification Revision 2.2.
These devices are also large enough to support PCI intellectual property (IP) cores.
Table 2–5
specifications.
CCIO
is 3.3 V, Bank 3 can support LVTTL, LVCMOS, and 3.3-V PCI. V
shows the MAX II device speed grades that meet the PCI timing
All I/O Banks Support
■
■
■
■
except for PCI. These pins reside in Bank 1 for all MAX II
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
I/O Bank 2
I/O Bank 4
CCIO
(Note
pins that determine the voltage standard support
CCIO
1),
for input and output pins. For example, when
(2)
© October 2008 Altera Corporation
I/O Bank 3
CCIO
Also Supports
the 3.3-V PCI
I/O Standard
Chapter 2: MAX II Architecture
setting for Bank 1.
CCIO
powers both
I/O Structure