EPM3512AQC208-10N Altera, EPM3512AQC208-10N Datasheet - Page 32
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EPM3512AQC208-10N
Manufacturer Part Number
EPM3512AQC208-10N
Description
IC MAX 3000A CPLD 512 208-PQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3512AQC208-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
172
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 3000A
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
32
# I/os (max)
172
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1994
EPM3512AQC208-10N
EPM3512AQC208-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3512AQC208-10N
Manufacturer:
ALTERA
Quantity:
42
Company:
Part Number:
EPM3512AQC208-10N
Manufacturer:
ALTERA44
Quantity:
3 415
Part Number:
EPM3512AQC208-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 3000A Programmable Logic Device Family Data Sheet
32
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
Symbol
CLR
PIA
LPA
Symbol
PD1
PD2
SU
H
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
Table 19. EPM3064A Internal Timing Parameters (Part 2 of 2)
Table 20. EPM3128A External Timing Parameters
Register clear time
PIA delay
Low–power adder
Input to non–
registered output
I/O input to non–
registered output
Global clock setup
time
Global clock hold time
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output
delay
Array clock high time
Array clock low time
Minimum pulse width
for clear and preset
Minimum global clock
period
Maximum internal
global clock frequency
Minimum array clock
period
Parameter
Parameter
C1 = 35 pF
(2)
C1 = 35 pF
(2)
(2)
(2)
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(3)
(2)
(2),
(2)
Conditions
(4)
(2)
(5)
Conditions
192.3
Min
3.3
0.0
1.0
2.0
2.0
1.8
0.2
1.0
2.0
2.0
2.0
–5
Note (1)
Min
Max
5.0
5.0
3.4
4.9
5.2
5.2
–4
Max
1.3
1.0
3.5
129.9
Speed Grade
Min
3.0
3.0
4.9
0.0
1.0
2.8
0.3
1.0
3.0
3.0
3.0
Note (1)
Speed Grade
Min
–7
–7
Max
7.5
7.5
5.0
7.1
7.7
7.7
Max
2.1
1.7
4.0
98.0
Min
6.6
0.0
1.0
4.0
4.0
3.8
0.4
1.0
4.0
4.0
4.0
Min
Altera Corporation
–10
–10
Max
Max
10.2
10.2
2.9
2.3
5.0
6.6
9.4
10
10
Unit
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns