EPM1270F256C3 Altera, EPM1270F256C3 Datasheet - Page 76
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C3
Manufacturer Part Number
EPM1270F256C3
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
3.01205GHz
Propagation Delay Time
6.2ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1321
EPM1270F256C3
EPM1270F256C3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA
Quantity:
162
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
5–18
External Timing Parameters
Table 5–23. EPM240 Global Clock External I/O Timing Parameters
MAX II Device Handbook
Symbol
t
t
t
t
t
t
t
t
PD1
PD2
SU
H
CO
CH
CL
CNT
Worst case
pin-to-pin
delay
through 1
look-up table
(LUT)
Best case
pin-to-pin
delay
through
1 LUT
Global clock
setup time
Global clock
hold time
Global clock
to output
delay
Global clock
high time
Global clock
low time
Minimum
global clock
period for
16-bit
counter
Parameter
f
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in
For more information about each external timing parameters symbol, refer to the
Understanding Timing in MAX II Devices
Table 5–23
Condition
10 pF
10 pF
10 pF
—
—
—
—
—
shows the external I/O timing parameters for EPM240 devices.
Min
166
166
1.7
2.0
3.3
—
—
–3 Speed
0
Grade
Max
4.7
3.7
4.3
—
—
—
—
—
MAX II / MAX IIG
Table 5–27
Min
216
216
2.2
2.0
4.0
—
—
–4 Speed
0
Grade
Max
6.1
4.8
5.6
—
—
—
—
—
through
Min
266
266
2.7
2.0
5.0
—
—
–5 Speed
0
(Part 1 of 2)
chapter in the MAX II Device Handbook.
Grade
Table
Max
7.5
5.9
6.9
—
—
—
—
—
5–31.
Min
253
253
2.4
2.0
5.4
—
—
–6 Speed
0
Grade
Chapter 5: DC and Switching Characteristics
Max
7.9
5.8
6.6
—
—
—
—
—
© August 2009 Altera Corporation
Min
335
335
4.1
2.0
8.1
—
—
Timing Model and Specifications
–7 Speed
0
MAX IIZ
Grade
Max
12.0
7.8
8.1
—
—
—
—
—
Min
339
339
4.6
2.0
8.4
—
—
–8 Speed
0
Grade
Max
14.0
8.5
8.6
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ps
ps
ns