ATF750C-10JU Atmel, ATF750C-10JU Datasheet - Page 5
![IC CPLD 10NS 28PLCC](/photos/6/70/67044/453-28-plcc_sml.jpg)
ATF750C-10JU
Manufacturer Part Number
ATF750C-10JU
Description
IC CPLD 10NS 28PLCC
Manufacturer
Atmel
Series
ATF750C(L)r
Datasheet
1.ATF750C-7JC.pdf
(25 pages)
Specifications of ATF750C-10JU
Programmable Type
In System Programmable (min 1K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Macrocells
10
Number Of I /o
10
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Features
Programmable
Voltage
5V
Memory Type
CMOS
Number Of Product Terms Per Macro
8
Maximum Operating Frequency
90 MHz
Delay Time
10 ns
Number Of Programmable I/os
28
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Family Name
ATF750C
# Macrocells
10
Number Of Usable Gates
750
Frequency (max)
90MHz
Propagation Delay Time
10ns
# I/os (max)
10
Operating Supply Voltage (typ)
5V
In System Programmable
No
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
9. Bus-friendly Pin-keeper Input and I/Os
10. Input Diagram
11. I/O Diagram
0776L–PLD–11/08
All input and I/O pins on the ATF750C(L) have programmable “pin-keeper” circuits. If activated,
when any pin is driven high or low and then subsequently left floating, it will stay at that previous
high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels,
which causes unnecessary power consumption and system noise. The keeper circuits eliminate
the need for external pull-up resistors and eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the
logic compiler device selection menu. Please refer to the software compiler table for more
details. Once the pin-keeper circuits are disabled, normal termination procedures are required
for unused inputs and I/Os.
DATA
INPUT
OE
PROTECTION
V
CIRCUIT
CC
ESD
V
CC
100K
PROGRAMMABLE
PROGRAMMABLE
OPTION
OPTION
100K
V
CC
ATF750C(L)
I/O
5