CY37032P44-125AXC Cypress Semiconductor Corp, CY37032P44-125AXC Datasheet - Page 6

• Manufacturer Part Number: CY37032P44-125AXC
• Description: IC CPLD 32 MACROCELL 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultra37000™r

Specifications of CY37032P44-125AXC

• Number Of Macrocells: 32
• Package / Case: 44-LQFP
• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of I /o: 37
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Features: Programmable
• Voltage: 5V
• Memory Type: CMOS
• Number Of Product Terms Per Macro: 16
• Maximum Operating Frequency: 125 MHz
• Delay Time: 10 ns
• Number Of Programmable I/os: 37
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• No. Of Macrocells: 32
• No. Of I/o's: 37
• Propagation Delay: 6ns
• Frequency: 125MHz
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Family Name: Ultra 37000
• # Macrocells: 32
• Number Of Usable Gates: 960
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 2
• # I/os (max): 37
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2901; CY37032P44-125AXC

Document Number : 38-03007 Rev. *H
FROM PTM
PRODUCT
FROM PTM
PRODUCT
TERMS
TERMS
0
0


ASYNCHRONOUS
16
16
BLOCK RESET
ASYNCHRONOUS
BLOCK PRESET
POLARITY MUXES
FROM CLOCK
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
4
4
0
2
3
0
2
3
C0 C1 C24
1
C0
1
C1
0
1
2
3
C10
C24
O
Q
INPUT PIN
C11
C25
C25
Figure 2. I/O and Buried Macrocells
O
0
1
1
0
0
1
1
0
Figure 3. Input Macrocell
BURIED MACROCELL
0
1
I/O MACROCELL
C7
D/T/L
O
D
D
LE
P
R
FEEDBACK TO PIM
Q
FEEDBACK TO PIM
FEEDBACK TO PIM
Q
Q
D/T/L
DECODE
C2 C3
0
1
P
R
Q
O
DECODE
C2 C3
0
1
D
O
Q
0
1
C4
Ultra37000 CPLD Family
O
“0”
“1”
SLOW
FAST
OE0 OE1
0
1
2
3
C12 C13
0
1
2
3
SLEW
C6 C5
O
C26
O
TO PIM
I/O CELL
Page 6 of 43
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