EPM240GT100I5N Altera, EPM240GT100I5N Datasheet - Page 34
![IC MAX II CPLD 240 LE 100-TQFP](/photos/6/70/67055/544-100-tqfp_sml.jpg)
EPM240GT100I5N
Manufacturer Part Number
EPM240GT100I5N
Description
IC MAX II CPLD 240 LE 100-TQFP
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM240GT100I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.7ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
240
Number Of Macrocells
192
Number Of I /o
80
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
1.8V
Memory Type
FLASH
Number Of Logic Elements/cells
240
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2275
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM240GT100I5N
Manufacturer:
ALTERA30
Quantity:
6 876
Part Number:
EPM240GT100I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–26
Figure 2–21. Column I/O Block Connection to the Interconnect
Note to
(1) Each of the four IOEs in the column I/O block can have one data_out or fast_out output, one OE output, and one data_in input.
I/O Standards and Banks
MAX II Device Handbook
Figure
Local Interconnect
2–21:
I/O Block
LAB Local
Interconnect
Figure 2–21
MAX II device IOEs support the following I/O standards:
■
■
■
■
■
R4 Interconnects
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
data_out
C4 Interconnects
[3..0]
shows how a column I/O block connects to the logic array.
LAB
4
[3..0]
OE
4
Column I/O Block
Interconnect
LAB Local
Interconnect
fast_out
Fast I/O
(Note 1)
[3..0]
Path
LAB
4
LAB Column
Clock [3..0]
4
data_in
[3..0]
C4 Interconnects
© October 2008 Altera Corporation
Column I/O
Block Contains
Up To 4 IOEs
LAB Local
Interconnect
Chapter 2: MAX II Architecture
LAB
I/O Structure