EPM7064AETC100-10N Altera, EPM7064AETC100-10N Datasheet - Page 37

• Manufacturer Part Number: EPM7064AETC100-10N
• Description: IC MAX 7000 CPLD 64 100-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7064AETC100-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 68
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Family Name: MAX 7000A
• # Macrocells: 64
• Number Of Usable Gates: 1250
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 68
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Cpld Type: EEPROM
• No. Of Macrocells: 64
• No. Of I/o's: 84
• Propagation Delay: 10ns
• Global Clock Setup Time: 6.2ns
• Frequency: 100MHz
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2007; EPM7064AETC100-10N

Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
Symbol
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 19. EPM7064AE External Timing Parameters
Input to non-
registered output
I/O input to non-
registered output
Global clock setup
time
Global clock hold time
Global clock setup
time of fast input
Global clock hold time
of fast input
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output
delay
Array clock high time
Array clock low time
Minimum pulse width
for clear and preset
Minimum global clock
period
Maximum internal
global clock frequency
Minimum array clock
period
Maximum internal
array clock frequency
Parameter
C1 = 35 pF
(2)
C1 = 35 pF
(2)
(2)
(2)
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(3)
(2)
(2),
(2)
(2),
Conditions
(4)
(4)
222.2
222.2
Min
2.8
0.0
2.5
0.0
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
2.0
-4
MAX 7000A Programmable Logic Device Data Sheet
Note (1)
Max
4.5
4.5
3.1
4.3
4.5
4.5
135.1
135.1
Speed Grade
Min
4.7
0.0
3.0
0.0
1.0
3.0
3.0
2.6
0.4
1.0
3.0
3.0
3.0
-7
Max
7.5
7.5
5.1
7.2
7.4
7.4
100.0
100.0
Min
6.2
0.0
3.0
0.0
1.0
4.0
4.0
3.6
0.6
1.0
4.0
4.0
4.0
-10
Max
10.0
10.0
10.0
10.0
7.0
9.6
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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