EPM7064BTC100-5 Altera, EPM7064BTC100-5 Datasheet - Page 12

• Manufacturer Part Number: EPM7064BTC100-5
• Description: IC MAX 7000 CPLD 64 100-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7064BTC100-5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.0ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1250
• Number Of I /o: 68
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

MAX 7000B Programmable Logic Device Data Sheet
12
Figure 5. MAX 7000B PIA Routing
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000B PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
control block for MAX 7000B devices. The I/O control block has
six or ten global output enable signals that are driven by the true or
complement of two output enable signals, a subset of the I/O pins, or a
subset of the I/O macrocells.
PIA Signals
CC
.
Figure 6
Altera Corporation
shows the I/O
To LAB