EPM7064LC68-12 Altera, EPM7064LC68-12 Datasheet - Page 29
![IC MAX 7000 CPLD 64 68-PLCC](/photos/6/71/67106/544-68-plcc_sml.jpg)
EPM7064LC68-12
Manufacturer Part Number
EPM7064LC68-12
Description
IC MAX 7000 CPLD 64 68-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7064LC68-12
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
12.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
52
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
125MHz
Propagation Delay Time
12ns
Number Of Logic Blocks/elements
4
# I/os (max)
52
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2301-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7064LC68-12
Manufacturer:
ALTERA
Quantity:
1 670
Company:
Part Number:
EPM7064LC68-12
Manufacturer:
ALTERA
Quantity:
20
Part Number:
EPM7064LC68-12
Manufacturer:
ALTERA
Quantity:
20 000
Part Number:
EPM7064LC68-12AA
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM7064LC68-12N
Manufacturer:
ALTERA
Quantity:
12 388
Figure 12. MAX 7000 Timing Model
Notes:
(1)
(2)
Altera Corporation
Only available in MAX 7000E and MAX 7000S devices.
Not available in 44-pin devices.
Delay
Input
t
I N
f
Delay
t
PIA
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
relationship of internal and external delay parameters.
For more infomration, see
Timing).
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
t
Delay
t
t
t
t
t
t
GLOB
SEXP
LAD
LAC
I C
EN
IOE
(1)
MAX 7000 Programmable Logic Device Family Data Sheet
Expander Delay
Application Note 94 (Understanding MAX 7000
Parallel
t
PEXP
Input Delay
Figure 13
Fast
t
F I N
(1)
Register
t
t
t
t
t
t
t
t
Delay
SU
H
PRE
CLR
RD
COMB
FSU
FH
shows the internal timing
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
X1
(2)
(2)
(1)
Delay
I/O
t
I O
29