EPM7128AETC144-10N Altera, EPM7128AETC144-10N Datasheet - Page 14

• Manufacturer Part Number: EPM7128AETC144-10N
• Description: IC MAX 7000 CPLD 128 144-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7128AETC144-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 2500
• Number Of I /o: 100
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 8
• Cpld Type: EEPROM
• No. Of Macrocells: 128
• No. Of I/o's: 100
• Propagation Delay: 10ns
• Global Clock Setup Time: 6.6ns
• Frequency: 98MHz
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MAX 7000A
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 100
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2030; EPM7128AETC144-10N

MAX 7000A Programmable Logic Device Data Sheet
Figure 6. I/O Control Block of MAX 7000A Devices
14
Note:
(1)
EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable
signals. EPM7512AE devices have 10 output enable signals.
PIA
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to V
enabled.
The MAX 7000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
From
Macrocell
Fast Input to
Macrocell
Register
To PIA
To Other I/O Pins
Open-Drain Output
Slew-Rate Control
6 or 10 Global
Output Enable Signals (1)
GND
VCC
OE Select Multiplexer
Altera Corporation
CC
, the output is