EPM7128AEFC100-10 Altera, EPM7128AEFC100-10 Datasheet - Page 8
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EPM7128AEFC100-10
Manufacturer Part Number
EPM7128AEFC100-10
Description
IC MAX 7000 CPLD 128 100-FBGA
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7128AEFC100-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-FBGA
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2025
EPM7128AEFC100-10
EPM7128AEFC100-10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128AEFC100-10
Manufacturer:
ALTERA
Quantity:
4
Part Number:
EPM7128AEFC100-10
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM7128AEFC100-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
Figure 2. MAX 7000A Macrocell
8
36 Signals
from PIA
LAB Local Array
Product Terms
16 Expander
Macrocells
MAX 7000A macrocells can be individually configured for either
sequential or combinatorial logic operation. The macrocells consist of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register.
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Product-
Select
Matrix
Term
Shared Logic
Expanders
Parallel Logic
Expanders
(from other
macrocells)
Global
Clear
Select
Clear
Clocks
Global
2
Figure 2
VCC
Enable
Clock/
Select
shows a MAX 7000A macrocell.
Fast Input
Select
ENA
D/T
CLRN
PRN
To PIA
Q
Altera Corporation
Programmable
Register
Register
Bypass
From
I/O pin
To I/O
Control
Block