EPM7064LC68-7 Altera, EPM7064LC68-7 Datasheet - Page 32
![IC MAX 7000 CPLD 64 68-PLCC](/photos/6/71/67106/544-68-plcc_sml.jpg)
EPM7064LC68-7
Manufacturer Part Number
EPM7064LC68-7
Description
IC MAX 7000 CPLD 64 68-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7064LC68-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
52
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2303-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7064LC68-7
Manufacturer:
ALTERA
Quantity:
2 300
Company:
Part Number:
EPM7064LC68-7
Manufacturer:
ALTERA
Quantity:
57
Company:
Part Number:
EPM7064LC68-7
Manufacturer:
ALTERA
Quantity:
5 510
Part Number:
EPM7064LC68-7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM7064LC68-7N
Manufacturer:
ALTERA
Quantity:
12 388
MAX 7000 Programmable Logic Device Family Data Sheet
32
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 20. MAX 7000 & MAX 7000E Internal Timing Parameters
Symbol
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off, V
Output buffer and pad delay
Slow slew rate = off, V
Output buffer and pad delay
Slow slew rate = on,
V
Output buffer enable delay
Slow slew rate = off, V
Output buffer enable delay
Slow slew rate = off, V
Output buffer enable delay
Slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
CCIO
CCIO
= 5.0 V or 3.3 V
= 5.0 V or 3.3 V
Parameter
CCIO
CCIO
CCIO
CCIO
= 5.0 V
= 3.3 V
= 5.0 V
= 3.3 V
(2)
(2)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
(2)
(2)
(8)
Conditions
(7)
(2)
(7)
(2)
Speed Grade -6
Min
3.0
1.5
2.5
0.5
Note (1)
Max
10.0
0.4
0.4
0.8
3.5
0.8
2.0
2.0
2.0
2.5
7.0
4.0
4.5
9.0
4.0
0.8
0.8
2.5
2.0
0.8
2.0
2.0
0.8
Speed Grade -7
Min
3.0
2.0
3.0
0.5
Altera Corporation
10.0
Max
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
2.5
7.0
4.0
4.5
9.0
4.0
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns