EPM1270F256I5 Altera, EPM1270F256I5 Datasheet - Page 11

IC MAX II CPLD 1270 LE 256-FBGA

EPM1270F256I5

Manufacturer Part Number
EPM1270F256I5
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Datasheets

Specifications of EPM1270F256I5

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
1.8797GHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1381
EPM1270F256I5

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Chapter 2: MAX II Architecture
Functional Description
Table 2–1. MAX II Device Resources
Figure 2–2. MAX II Device Floorplan
Note to
(1) The device shown is an EPM570 device. EPM1270 and EPM2210 devices have a similar floorplan with more LABs. For EPM240 devices, the CFM
© October 2008 Altera Corporation
EPM240
EPM570
EPM1270
EPM2210
Note to
(1) The width is the number of LAB columns in length.
and UFM blocks are located on the left side of the device.
Devices
Figure
Table
Logic Array
I/O Blocks
I/O Blocks
I/O Blocks
2 GCLK
2–2:
2–1:
Inputs
Blocks
UFM Blocks
Figure 2–2
1
1
1
1
shows a floorplan of a MAX II device.
(Note 1)
LAB Columns
12
16
20
6
Long LAB Rows
10
4
4
7
LAB Rows
CFM Block
Short LAB Rows
UFM Block
(Width)
3 (3)
3 (5)
3 (7)
(1)
Total LABs
127
221
24
57
MAX II Device Handbook
2 GCLK
Inputs
Logic Array
Blocks
2–3

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