EPM7128SQC160-10 Altera, EPM7128SQC160-10 Datasheet - Page 9

IC MAX 7000 CPLD 128 160-PQFP

EPM7128SQC160-10

Manufacturer Part Number
EPM7128SQC160-10
Description
IC MAX 7000 CPLD 128 160-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7128SQC160-10

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
100
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-MQFP, 160-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Family Name
MAX 7000S
# Macrocells
128
Number Of Usable Gates
2500
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
8
# I/os (max)
100
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2327

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Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
Altera Corporation
36 Signals
from PIA
Logic Array
Product Ter
16 Expander
T T ms
Each LAB is fed by the following signals:
Macrocells
The MAX 7000 macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, and EPM7096 devices is shown in
Product-
Select
Matrix
Ter
T T m
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices
Shared Logic
Expanders
Parallel Logic
Expanders
(from other
macrocells)
MAX 7000 Programmable Logic Device Family Data Sheet
Global
Clear
Select
Clear
Global
Clocks
2
VCC
Enable
Clock/
Select
Fast Input
Select
D/T
ENA
Figure
CLRN
PRN
to PIA
Q
Programmable
Register
Register
3.
Bypass
From
I/O pin
To I/O
Control
Block
9

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