EPM7192SQC160-10N Altera, EPM7192SQC160-10N Datasheet - Page 22
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EPM7192SQC160-10N
Manufacturer Part Number
EPM7192SQC160-10N
Description
IC MAX 7000 CPLD 192 160-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7192SQC160-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
12
Number Of Macrocells
192
Number Of Gates
3750
Number Of I /o
124
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-MQFP, 160-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
12
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2054
EPM7192SQC160-10N
EPM7192SQC160-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7192SQC160-10N
Manufacturer:
ALTERA31
Quantity:
921
Part Number:
EPM7192SQC160-10N
Manufacturer:
ALTERA
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
22
SAMPLE/PRELOAD
EXTEST
BYPASS
IDCODE
ISP Instructions
Table 9. MAX 7000 JTAG Instructions
JTAG Instruction
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Devices
MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std.
1149.1-1990.
MAX 7000 family. The pin-out tables (see the Altera web site
(http://www.altera.com) or the Altera Digital Library for pin-out
information) show the location of the JTAG control pins for each device.
If the JTAG interface is not required, the JTAG pins are available as user
I/O pins.
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which
allows the BST data to pass synchronously through a selected device
to adjacent devices during normal device operation.
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
These instructions are used when programming MAX 7000S devices
via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster
download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc),
or Serial Vector Format file (.svf) via an embedded processor or test
equipment.
Table 9
describes the JTAG instructions supported by the
Description
Altera Corporation