EPM7512BFC256-5 Altera, EPM7512BFC256-5 Datasheet - Page 31

• Manufacturer Part Number: EPM7512BFC256-5
• Description: IC MAX 7000 CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7512BFC256-5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Family Name: MAX 7000B
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 166.67MHz
• Propagation Delay Time: 5.5ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 212
• Operating Supply Voltage (typ): 2.5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2361

Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) The POR time for all 7000B devices does not exceed 100 μs. The sufficient V
(11) These devices support in-system programming for –40° to 100° C. For in-system programming support between
Altera Corporation
Symbol
C
C
Table 17. MAX 7000B Device Capacitance
IN
I/O
See the
Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V
for input currents less than 100 mA and periods shorter than 20 ns.
All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before V
powered.
These values are specified under the Recommended Operating Conditions in
The parameter is measured with 50% of the outputs each sourcing the specified current. The I
to high-level TTL or CMOS output current.
The parameter is measured with 50% of the outputs each sinking the specified current. The I
low-level TTL or CMOS output current.
This value is specified for normal device operation. During power-up, the maximum leakage current is ±300
This pull-up exists while devices are being programmed in-system and in unprogrammed devices during
power-up. The pull-up resistor is from the pins to V
Capacitance is measured at 25° C and is sample-tested only. Two of the dedicated input pins (
a maximum capacitance of 15 pF.
The device is fully initialized within the POR time after V
–40° and 0° C, contact Altera Applications.
Input pin capacitance
I/O pin capacitance
Operating Requirements for Altera Devices Data
Parameter
V
V
IN
OUT
= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz
Note (9)
CCIO
Sheet.
MAX 7000B Programmable Logic Device Data Sheet
.
Conditions
CCINT
reaches the sufficient POR voltage level.
CCINT
Table 15 on page
voltage level for POR is 2.375 V.
CCINT
Min
OL
OE1
and V
OH
parameter refers to
29.
parameter refers
and
Max
CCIO
8
8
GCLRN
are
Unit
) have
pF
pF
μ
31
A.